MAX1463CAI 데이터 시트보기 (PDF) - Maxim Integrated

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MAX1463CAI

Low-Power Two-Channel Sensor Signal Processor

Maxim Integrated 

Low-Power Two-Channel Sensor

Signal Processor

VDD

VDDF

INPn

OUTnSM

100Ω

5VDC

OUT

SENSOR

MAX1463

INMn

0.47µF 0.1µF 100pF

VSS

GND

Figure 2. Basic Bridge Sensor Ratiometric Output Configuration

old, all internal CPU registers are set to their POR

default state. Power-on control bits for internal modules

are reset to the OFF condition.

CPU Architecture

The CPU provides a wide range of functionality to be

incorporated in an embedded system. The CPU can

compensate nonlinear and temperature-dependent sen-

sors, check for over/underlimit conditions, output sensor

or temperature data as an analog signal or pulse-width-

modulated digital signal, and execute control strategies.

The CPU can perform a limited amount of signal pro-

cessing (filtering). A timer is included so that uniform

sampling (equally spaced ADC conversions) of the

input sensors can be performed.

The CPU registers and ports are implemented in

volatile, static memory. There are several registers con-

tained in various peripheral modules that provide mod-

ule configuration settings, control functions, and data.

These module registers are accessible through an indi-

rect addressing scheme as described in detail in the

CPU Registers, CPU Ports, and Modules sections.

Figure 3 shows the CPU architecture.

CPU Registers

The MAX1463 incorporates a CPU with 16 internal reg-

isters. All of the CPU registers have a 16-bit data word

width. Five of the 16 registers have predefined function-

al operation dependent on the instruction being execut-

ed. The remaining registers are general purpose.

The CPU registers are embedded in the CPU itself and

are not all directly accessible by the serial interface.

The accumulator register (A), the pointer register (P),

and the instruction (FLASH data) can be read through

the serial interface when the CPU is halted. This

enables a single-step mode of code execution to ease

code writing and debugging. A special program

instruction sequence is required to observe the other

CPU registers. Table 1 lists the CPU registers.

CPU Ports

The MAX1463 incorporates 16 CPU ports that are directly

accessible by the serial interface. All the CPU ports have

a 16-bit data-word width. The contents of the ports can

be read and written by transferring data to and from the

accumulator register (A) using the RDX and WRX instruc-

tions. No other CPU instructions act on the CPU ports.

Three CPU ports PD, PE, and PF have uniquely defined

operation for reading and writing data to and from the

peripheral modules. All CPU ports are static and volatile.

Table 2 lists the CPU ports.

Modules

The MAX1463 modules are the functional blocks used to

process analog and digital signals to and from the CPU.

Each module is addressed through CPU ports PD, PE,

and PF, as described in the CPU Ports section. All mod-

ules use static, volatile registers for data retention. There

are three types of module registers: configuration, data,

and control. They are used to put a module into a partic-

ular mode of operation. Configuration registers hold con-

figuration bits that control static settings such as PGA

gain, coarse offset, etc. Data registers hold input data

such as DAC and PWM input words or output data such

as the result of an ADC conversion. Control registers are

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