MAX3680(1997) 데이터 시트보기 (PDF) - Maxim Integrated
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MAX3680 Datasheet PDF : 8 Pages
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+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
______________________________________________________________Pin Description
PIN
1, 2, 5, 8,
14, 18, 25
3
4
6
7
9, 11, 12, 16,
20, 23, 27
10
13
15, 17, 19, 21,
22, 24, 26, 28
NAME
VCC
SD+
SD-
SCLK+
SCLK-
GND
SYNC
PCLK
PD0–PD7
FUNCTION
+3.3V Supply Voltage
Noninverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition.
Inverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition.
Noninverting PECL Serial Clock Input
Inverting PECL Serial Clock Input
Ground
TTL Synchronization Pulse Input. Pulse high for at least two SCLK periods to shift the data align-
ment by dropping one bit in the serial input data stream.
TTL Parallel Clock Output
TTL Parallel Data Outputs. Data is updated on the falling edge of PCLK. See Figure 2 for the relation-
ship between serial-data-bit position and output-data-bit assignment.
_______________Detailed Description
The MAX3680 deserializer uses an 8-bit shift register,
8-bit parallel output register, 3-bit counter, PECL input
buffers, and TTL input/output buffers to convert
622Mbps serial data to 8-bit-wide, 77Mbps parallel
data (Figure 1).
The input shift register continuously clocks incoming
data on the positive transition of the serial clock (SCLK)
input signal. The 3-bit counter generates a parallel out-
put clock (PCLK) by dividing down the serial clock fre-
quency. The PCLK signal is used to clock the parallel
output register. During normal operation, the counter
divides the SCLK frequency by eight, causing the out-
put register to latch every eight bits of incoming serial
data.
The synchronization input (SYNC) is used for data
realignment and reframing. When the SYNC signal is
pulsed high for at least two SCLK cycles, PCLK is
delayed by one SCLK cycle, causing the first incoming
bit of the serial input data stream to be dropped. This
realignment is guaranteed to occur within two PCLK
cycles of the SYNC rising edge.
See Figure 2 for the functional timing diagrams and
Figure 3 for the timing parameters diagram.
SD+
PECL
SD-
SCLK+
PECL
SCLK-
SYNC
TTL
TTL
TTL
8-BIT
SHIFT
REGISTER
TTL
TTL
8-BIT
PARALLEL
OUTPUT
REGISTER
TTL
TTL
MAX3680
TTL
TTL
3-BIT
COUNTER
TTL
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PCLK
Figure 1. Functional Diagram
4 _______________________________________________________________________________________
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