MC68160BFB 데이터 시트보기 (PDF) - Motorola => Freescale

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MC68160BFB

ENHANCED ETHERNET INTERFACE TRANSCEIVER

Motorola => Freescale 

TPTX+/–

MC68160 MC68160B MC68160C

Figure 29. TPTX SQE (CLSN) Timing (End of Frame)

2V

TPSQEL

CLSN

1.5V

t173

t171

t170

t172

1.5V

1.5V

TP RECEIVE SWITCHING

Characteristic

Symbol

Min

Differential Input Voltage Range Unconditional Squelch (Note 1)

(1.8 V < Input Common Mode Voltage < 3.2 V)

VIDFSTP

0

Positive or Negative Differential Input Pulse Width for Conditional Receive Unsquelch

t180

20

(See Figure 31)

TPRX to RCLK Bit Loss at start of packet (See Figure 32)

TPRX to RCLK Steady State Propagation Delay (See Figure 32)

TPRX to RX Start Up Delay (See Figure 32)

TPRX held high from last valid positive transition (See Figure 33)

RENA Deassertion Delay from last valid positive transition of TPRX Pair

(MC68160, MC68160C) (See Figure 33)

t181

–

t182

–

t183

–

t186

230

t187

–

RENA Deassertion Delay from last valid positive transition of TPRX Pair (MC68160B)

t187

–

TP RECEIVE LINK INTEGRITY SWITCHING

Required Pulse Width Range to be recognized as a Link Pulse (Note 2)

t200

50

Last TPRX activity to high state TPLIL Output

(Receive Link Loss Timeout Interval)

t201

100

Receive Link Beat Separation

Minimum Range (Note 3)

Maximum Range (Note 4)

t202

3.0

t203

100

NOTES: 1. Measured with Test Load H attached to the receive pins.

2. Measured at the receive pins.

3. Link beats closer in time to this range of values are considered noise, and are rejected.

4. Link beats further apart in time than this range of values are not considered consecutive, and are rejected.

Max

Unit

|264|

mV

30

ns

10

Bits

400

ns

1.5

µs

–

ns

350

ns

400

ns

200

ns

150

ms

ms

7.0

150

Figure 30. Test Load H

1.0µH

200µH

100Ω

100pF 100pF

Line

1.0µH

Figure 31. TPRX Input Switching

0mV

TPRX

t180

–330mV

+330mV

t180

MOTOROLA ANALOG IC DEVICE DATA

21

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