MU9C8148 데이터 시트보기 (PDF) - MUSIC Semiconductors
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MU9C8148 Datasheet PDF : 24 Pages
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MU9C8148
No. Symbol
13 tSHSL
14 tSLKL
15 tKHKL
16 tAVKL
17 tKLAX
18 tKLWRL
19 tWLBDL
20 tWLBEL
21 tBDLBEL
22 tWLDV
23 tWLRDL
24 tRDLDX
25 tRDLWRH
26 tRWHWRL
27 tWHBDH
28 tWHBEH
29 tRWHRDH
30 tRWHRDZ
31 tSHRDZ
32 tRLBEL
33 tRLRDL
34 tDVRDL
35 tRHBEH
36 tRHDZ
No. Symbol
37 tSHSL
38 tSLDSL
39 tSRVDSL
40 tAVDSL
41 tDSLBDV
42 tDSLBEL
43 tBDLBEL
44 tDSLDV
45 tDSLRDL
46 tRDLDX
47 tRDLDSH
48 tDSHDSL
49 tDSHSRX
50 tDSHAX
51 tDSHBDX
Rev. 5.5 Draft web
SWITCHING CHARACTERISTICS (CONT’D)
Host Processor Interface Switching Characteristics
Intel Mode Timing
Parameter
Min
Max
/CS HIGH Pulse Width
0
/CS LOW to ALE LOW Setup Time
2
ALE HIGH Pulse Width
2
Address Bus Valid to ALE LOW Setup Time
2
Address Bus Invalid from ALE LOW Hold Time
5
ALE LOW to /WS or /RS LOW Setup Time
0
/WS LOW to /HBDIR LOW Delay Time
tCLCL + 3
/WS LOW to /HBEN LOW Delay Time
tCLCL + 3
/HBDIR LOW to /HBEN LOW Delay Time
10
/WS LOW to Data Input Valid Delay Time
3 •tCLCL
/WS LOW to /HBRDY LOW Delay Time
3 • tCLCL + 3
/HBRDY LOW to Data Input Invalid Hold Time
tCLCL
/HBRDY LOW to /WS or /RS HIGH Setup Time
0
/WS or /RS HIGH Pulse Width
2 • tCLCL
/WS HIGH to /HBDIR HIGH Delay Time
tCLCL + 3
2 • tCLCL + 20
/WS HIGH to /HBEN HIGH Delay Time
tCLCL + 3
2 • tCLCL + 20
/WS or /RS HIGH to /HBRDY HIGH Delay Time
3
tCLCL + 20
/WS or /RS HIGH to /HBRDY Hi-Z Delay Time
tCLCL + 3
2 • tCLCL + 20
/CS HIGH to /HBRDY Hi-Z Delay Time
tCLCL + 3
tCLCL + 20
/RS LOW to /HBEN LOW Delay Time
2 • tCLCL + 3
/RS LOW to /HBRDY LOW Delay Time
3 • tCLCL + 3
Data Output Valid to /HBRDY LOW Setup Time
2
/RS HIGH to /HBEN HIGH Delay Time
tCLCL + 3
2 • tCLCL + 20
/RS HIGH to Data Output Hi-Z Delay Time
tCLCL + 3
Motorola Mode Timing
2 • tCLCL + 20
Parameter
Min
Max
/CS HIGH Pulse Width
0
/CS LOW to /UDS or /LDS LOW Setup Time
0
SRNW Valid to /UDS or /LDS LOW Setup Time
2
Address Bus Valid to /UDS or /LDS LOW Setup
2
/UDS or /LDS LOW to /HBDIR LOW Delay Time
tCLCL + 3
/UDS or /LDS LOW to /HBEN LOW Delay Time
R • tCLCL + 3
/HBDIR LOW to HBEN LOW Delay Time
10
/UDS or /LDS LOW to Data Input Valid Delay
3 •tCLCL
/UDS or /LDS LOW to /HBRDY LOW Delay Time 3 • tCLCL + 3
/HBRDY LOW to Data Input Invalid Hold Time
tCLCL
/HBRDY LOW to /UDS or /LDS HIGH Setup Time
0
/UDS or /LDS HIGH Pulse Width
2 • tCLCL
/UDS or /LDS HIGH to SRNW Invalid Hold Time
0
/UDS or /LDS HIGH to Address Bus Invalid Hold
10
/UDS or /LDS HIGH to /HBDIR Invalid Delay
tCLCL + 3
2 • tCLCL + 20
18
Units Notes
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns 1, 2
ns
ns
ns
ns
ns
ns
ns
ns
ns 1
ns 1, 3
ns
ns
ns
Units Notes
ns
ns
ns
ns
ns
ns 1, 4
ns
ns
ns 1, 5
ns
ns
ns
ns
ns
ns
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