NCP3418(2004) 데이터 시트보기 (PDF) - ON Semiconductor
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NCP3418 Datasheet PDF : 10 Pages
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NCP3418, NCP3418A
APPLICATIONS INFORMATION
Theory of Operation
The NCP3418 and NCP3418A are single phase MOSFET
drivers optimized for driving two N−channel MOSFETs in
a synchronous buck converter topology. The NCP3418
features an internal diode, while the NCP3418A requires an
external BST diode for the floating top gate driver. A single
PWM input signal is all that is required to properly drive the
high−side and the low−side MOSFETs. Each driver is
capable of driving a 3.3 nF load at frequencies up to 500 kHz.
Low−Side Driver
The low−side driver is designed to drive a
ground−referenced low RDS(on) N−Channel MOSFET. The
voltage rail for the low−side driver is internally connected to
the VCC supply and PGND.
When the NCP3418 is enabled, the low−side driver’s
output is 180_ out of phase with the PWM input. When the
device is disabled, the low−side gate is held low.
High−Side Driver
The high−side driver is designed to drive a floating low
RDS(on) N−channel MOSFET. The bias voltage for the high
side driver is developed by a bootstrap circuit referenced to
SW. The bootstrap capacitor should be connected between
the BST and SW pins.
The bootstrap circuit comprises an internal or external
diode, D1 (in which the anode is connected to VCC), and an
external bootstrap capacitor, CBST. When the NCP3418 is
starting up, the SW pin is at ground, so the bootstrap capacitor
will charge up to VCC through D1. When the PWM input goes
high, the high−side driver will begin to turn on the high−side
MOSFET by pulling charge out of CBST. As the high−side
MOSFET turns on, the SW pin will rise to VIN, forcing the
BST pin to VIN + VCC, which is enough gate−to−source
voltage to hold the MOSFET on. To complete the cycle, the
high−side MOSFET is switched off by pulling the gate down
to the voltage at the SW pin. When low−side MOSFET turns
on, the SW pin is held at ground. This allows the bootstrap
capacitor to charge up to VCC again.
The high−side driver’s output is in phase with the PWM input.
When the device is disabled, the high side gate is held low.
Safety Timer and Overlap Protection Circuit
The overlap protection circuit prevents both the high−side
MOSFET and the low−side MOSFET from being on at the
same time, and minimizes the associated off times. This will
reduce power losses in the switching elements. The overlap
protection circuit accomplishes this by controlling the delay
from turning off the high−side MOSFET to turning on the
low−side MOSFET.
To prevent cross conduction during the high−side
MOSFET’s turn−off and the low−side MOSFET’s turn−on,
the overlap circuit monitors the voltage at the SW pin. When
the PWM input signal goes low, DRVH will go low after a
propagation delay (tpdlDRVH), turning the high−side
MOSFET off. However, before the low−side MOSFET can
turn on, the overlap protection circuit waits for the voltage at
the SW pin to fall below 4.0 V. Once SW falls below the 4.0 V
threshold, DRVL will go high after a propagation delay
(tpdhDRVL), turning the low−side MOSFET on. However, if
SW does not fall below 4.0 V in 300 ns, the safety timer
circuit will override the normal control scheme and drive
DRVL high. This will help insure that if the high−side
MOSFET fails to turn off it will not produce an over−voltage
at the output.
Similarly, to prevent cross conduction during the
low−side MOSFET’s turn−off and the high−side
MOSFET’s turn−on, the overlap circuit monitors the voltage
at the gate of the low−side MOSFET through the DRVL pin.
When the PWM signal goes high, DRVL will go low after
a propagation delay (tpdlDRVL), turning the low−side
MOSFET off. However, before the high−side MOSFET can
turn on, the overlap protection circuit waits for the voltage
at DRVL to drop below 1.5 V. Once this has occurred, DRVH
will go high after a propagation delay (tpdhDRVH), turning
the high−side MOSFET on.
Application Information
Supply Capacitor Selection
For the supply input (VCC) of the NCP3418, a local bypass
capacitor is recommended to reduce noise and supply peak
currents during operation. Use a 1.0 to 4.7 mF, low ESR
capacitor. Multilayer ceramic chip (MLCC) capacitors
provide the best combination of low ESR and small size.
Keep the ceramic capacitor as close as possible to the VCC
and PGND pins.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor
(CBST) and the internal (or an external) diode. Selection of
these components can be done after the high−side MOSFET
has been chosen.
The bootstrap capacitor must have a voltage rating that is
able to withstand twice the maximum supply voltage. A
minimum 50 V rating is recommended. The capacitance is
determined using the following equation:
CBST
+
QGATE
DVBST
(eq. 1)
where QGATE is the total gate charge of the high−side
MOSFET, and DVBST is the voltage droop allowed on the
high−side MOSFET drive. For example, a NTD60N03 has
a total gate charge of about 30 nC. For an allowed droop of
300 mV, the required bootstrap capacitance is 100 nF. A
good quality ceramic capacitor should be used.
If an external Schottky diode will be used for bootstrap,
it must be rated to withstand the maximum supply voltage
plus any peak ringing voltages that may be present on SW.
The average forward current can be estimated by:
IF(AVG) + QGATE fMAX
(eq. 2)
where fMAX is the maximum switching frequency of the
controller. The peak surge current rating should be checked
in−circuit, since this is dependent on the source impedance
of the 12 V supply and the ESR of CBST.
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