NE570(2003) 데이터 시트보기 (PDF) - Philips Electronics
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NE570 Datasheet PDF : 12 Pages
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Philips Semiconductors
Compandor
Product data
NE570
At very low input signal levels the bias current of Q2, (typically
50 nA), will become significant as it must be supplied by Q5.
Another low level error can be caused by DC coupling into the
rectifier. If an offset voltage exists between the VIN input pin and the
base of Q2, an error current of VOS/R1 will be generated. A mere
1 mV of offset will cause an input current of 100 nA, which will
produce twice the error of the input bias current. For highest
accuracy, the rectifier should be coupled into capacitively. At high
input levels the β of the PNP Q6 will begin to suffer, and there will be
an increasing error until the circuit saturates. Saturation can be
avoided by limiting the current into the rectifier input to 250 µA. If
necessary, an external resistor may be placed in series with R1 to
limit the current to this value. Figure 11 shows the rectifier accuracy
versys input level at a frequency of 1 kHz.
+1
0
–1
–40
–20
0
RECTIFIER INPUT dBm
SR00685
Figure 11. Rectifier accuracy
At very high frequencies, the response of the rectifier will fall off. The
roll-off will be more pronounced at lower input levels due to the
increasing amount of gain required to switch between Q5 or Q6
conducting. The rectifier frequency response for input levels of
0 dBm, –20 dBm, and –40 dBm is shown in Figure 12. The response
at all three levels is flat to well above the audio range.
INPUT = 0 dBm
0
–20 dBm
3
–40 dBm
10 k
1 MEG
FREQUENCY (Hz)
SR00686
Figure 12. Rectifier frequency response versus input level
VARIABLE GAIN CELL
Figure 13 is a diagram of the variable gain cell. This is a linearized
two-quadrant transconductance multiplier. Q1, Q2 and the op amp
provide a predistorted drive signal for the gain control pair, Q3 and
Q4. The gain is controlled by IG and a current mirror provides the
output current.
The op amp maintains the base and collector of Q1 at ground
potential (VREF) by controlling the base of Q2. The input current IIN
(= VIN/R2) is thus forced to flow through Q1 along with the current
I1, so IC1 = I1 + IIN. Since I2 has been set at twice the value of I1, the
current through Q2 is:
I2 – (I1 + IIN) = I1 – IIN = IC2.
The op amp has thus forced a linear current swing between Q1 and
Q2 by providing the proper drive to the base of Q2. This drive signal
will be linear for small signals, but very non-linear for large signals,
since it is compensating for the non-linearity of the differential pair,
Q1 and Q2, under large signal conditions.
V+
I1
140 µA
–
+
R2
20 kΩ
VIN
Q1 Q2
IIN
I2 ( = 2 I1 )
280 µA
Q3
Q4
IG
NOTE:
V–
IOUT =
IG
I1 IIN =
IG VIN
I1 R2
SR02514
Figure 13. Simplified ∆G Cell Schematic
The key to the circuit is that this same predistorted drive signal is
applied to the gain control pair, Q3 and Q4. When two differential
pairs of transistors have the same signal applied, their collector
current ratios will be identical regardless of the magnitude of the
currents. This gives us:
IC1
IC2
+
IC4
IC3
+
I1 ) IIN
I1 * IIN
plus the relationships IG = IC3 + IC4 and IOUT = IC4 – IC3 will yield the
multiplier transfer function,
IOUT
+
IG
I1
IIN
+
VIN IG
R2 I1
This equation is linear and temperature-insensitive, but it assumes
ideal transistors.
If the transistors are not perfectly matched, a parabolic, non-linearity
is generated, which results in second harmonic distortion. Figure 14
gives an indication of the magnitude of the distortion caused by a
given input level and offset voltage. The distortion is linearly
proportional to the magnitude of the offset and the input level.
Saturation of the gain cell occurs at a +8dBm level. At a nominal
operating level of 0dBm, a 1mV offset will yield 0.34% of second
harmonic distortion. Most circuits are somewhat better than this,
2003 Apr 03
7
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