AD1671S 데이터 시트보기 (PDF) - Analog Devices
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AD1671S Datasheet PDF : 16 Pages
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AD1671
UNIPOLAR (0 V TO +2.5 V) CALIBRATION
The connections for the 0 V to +2.5 V input range calibration is
shown in Figure 11. Figure 11 shows an example of how the
offset error can be trimmed in front of the AD1671. The proce-
dure for trimming the offset and gain errors is the same as for
the unipolar 5 V range.
+15V
VIN
0 TO +2.5V
GAIN R2
ADJ 2k
10k
390Ω
OFFSET ADJ
R1
1kΩ
AD845
1k
AIN1 5k
AIN2 5k
SHA
10k
SHA OUT
AD1671
BPO/UPO
REF IN
REF OUT
1µF
and tSS minimum). To satisfy the requirements of the 574 type
latch the recommended logic families are S, AS, ALS, F or
BCT. New data from the AD1671 is latched on the rising edge
of the DAV (Pin 16) output pulse. Previous data can be latched
by inverting the DAV output with a 7404 type inverter.
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
DAV
74HC574
1D
1Q
2D
2Q
3D
3Q
4D
4Q
5D
5Q
6D
6Q
7D
7Q
8D
8Q
CLOCK OC
DATA BUS
BIT 9
BIT 10
BIT 11
BIT 12
AD1671
74HC574
1D
1Q
2D
2Q
3D
3Q
4D
4Q
5D
5Q
6D
6Q
7D
7Q
8D
8Q
CLOCK OC
3-STATE
CONTROL
Figure 13. AD1671 to Output Latches
Figure 11. Unipolar (0 V to +2.5 V) Calibration
BIPOLAR (؎2.5 V) CALIBRATION
The connections for the bipolar ± 2.5 V input range is shown in
Figure 12.
+15V
VIN
–2.5V TO +2.5V
GAIN R2
ADJ 2k
10k
390Ω
OFFSET ADJ
R1
1kΩ
AD845
AIN1 5k
AIN2 5k
1k
SHA
10k
SHA OUT
AD1671
BPO/UPO
REF IN
REF OUT
1µF
Figure 12. Bipolar (±2.5 V) Calibration
OUTPUT LATCHES
Figure 13 shows the AD1671 connected to the 74HC574 octal
D-type edge-triggered latches with 3-state outputs. The latch
can drive highly capacitive loads (i.e., bus lines, I/O ports) while
maintaining the data signal integrity. The maximum setup and
hold times of the 574 type latch must be less than 20 ns (tDD
OUT OF RANGE
An out-of-range condition exists when the analog input voltage
is beyond the input range (0 V to +2.5 V, 0 V to +5 V, ± 2.5 V,
± 5 V) of the converter OTR (Pin 15) is set low when the analog
input voltage is within the analog input range. OTR is set HIGH
and will remain HIGH when the analog input voltage exceeds
the input range by typically 1/2 LSB (OTR transition is tested to
± 6 LSBs of accuracy) from the center of the ± full-scale output
codes. OTR will remain HIGH until the analog input is within
the input range and another conversion is completed. By logical
ANDing OTR with the MSB and its complement, overrange
high or underrange low conditions can be detected. Table II is a
truth table for the over/under range circuit in Figure 14. Sys-
tems requiring programmable gain conditioning prior to the
AD1671 can immediately detect an out-of-range condition, thus
eliminating gain selection iterations.
Table II. Out-of-Range Truth Table
OTR
MSB
Analog Input Is
0
0
In Range
0
1
In Range
1
0
Underrange
1
1
Overrange
MSB
OTR
OVER = "1"
MSB
UNDER = "1"
Figure 14. Overrange or Underrange Logic
–10–
REV. B
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