MCF5207/8 Device Configurations
1 MCF5207/8 Device Configurations
The following table compares the two devices described in this document:
Table 1. MCF5207 & MCF5208 Configurations
Module
MCF5207 MCF5208
Version 2 ColdFire Core with EMAC
(Enhanced Multiply-Accumulate Unit)
Core (System) Clock
Peripheral and External Bus Clock
(Core clock ÷ 2)
Performance (Dhrystone/2.1 MIPS)
Instruction/Data Cache
x
x
up to 166.67 MHz
up to 83.33 MHz
up to 159
8 Kbytes
Static RAM (SRAM)
SDR/DDR SDRAM Controller
Fast Ethernet Controller (FEC)
Low-Power Management Module
16 Kbytes
x
x
—
x
x
x
UARTs
I2C
QSPI
32-bit DMA Timers
Watchdog Timer (WDT)
3
3
x
x
x
x
4
4
x
x
Periodic Interrupt Timers (PIT)
4
4
Edge Port Module (EPORT)
x
x
Interrupt Controllers (INTC)
1
1
16-channel Direct Memory Access (DMA)
x
x
FlexBus External Interface
General Purpose I/O Module (GPIO)
JTAG - IEEE® 1149.1 Test Access Port
Package
x
x
x
x
x
x
144 LQFP 160 QFP
144 MAPBGA 196 MAPBGA
MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 0.5
2
Preliminary
Freescale Semiconductor