µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
Figure 7-1. DMA Function Block Diagram
CPU
TCn
NMI
INTPmn
Request from on-chip
peripheral I/O
DMARQn
DMAAKn
Internal RAM
Internal peripheral I/O
Internal bus
Internal peripheral I/O bus
Data control Address control
Count control
Channel control
Bus interface
External bus
DMA source address
register (DSAnH/DSAnL)
DMA destination address
register (DDAnH/DDAnL)
DMA byte count register
(DBCn)
DMA addressing control
register (DADCn)
DMA channel control
register (DCHCn)
DMA disable status
register (DDISn)
DMA restart register
(DRSTn)
DMA trigger source
register (DTFRn)
DMAC
V850E/MS1
External I/O External RAM External ROM
Remark m = 10 to 15, n = 0 to 3
30
Preliminary Data Sheet U14168EJ2V0DS00