Table 6. SPI Register Table (Read/Write)
CNTL_REG: System Control Register
Addr. Name Type
B7
B6
B5
B4
B3
B2
B1
B0
0x00 CNTL W/R TMR_CLR OC_TMR2 OC_TMR1 OC_TMR0 IP_EA DT_EA CW FREE/nST
Reset
0
0
0
0
0
0
1
1
OC Timer Clear
b7 TMR_CLR
1=OC timer clear, 0=OC time is normal function
b[6:4]
OC_TMR[2:0]
Overload Current Protection Timer Configuration
000=OC timer configure by OC_TMR pin
001=OC timer configure to 2^18 ÷ fSYS
010=OC timer configure to 2^19 ÷ fSYS
011=OC timer configure to 2^20 ÷ fSYS
100=OC timer configure to 2^21 ÷ fSYS
101=OC timer configure to 2^22 ÷ fSYS
110=OC timer configure to 2^23 ÷ fSYS
111=OC timer configure to 2^24 ÷ fSYS
b3
IP_EA
IP_REG Enable
1=duty control by IP_REG, 0=duty control by IP pin
b2
DT_EA
DUTY_REG Enable
1=duty control by DUTY_REG, 0=duty control by DUTY pin
b1
CW
Output Driving Current Direction
1=CW, 0=CCW
b0
FREE/nST
FREE or START
1=FREE (PWM outputs disable), 0=START (PWM outputs enable)
PWM_REG: PWM Control Register
Addr. Name Type
B7
B6
B5
B4
B3
B2
B1
B0
0x01 PWM W/R PMOD
n/a DT1
DT0
SEQ_TBL SYNCOFF EXT_SYN LPWM
Reset
0
0
0
0
0
0
0
0
PWM Mode Select
b7
PMOD 0=
sine wave PWM drive after angle detector locked
1=
square wave PWM drive after angle detector locked
b[5:4]
DT[1:0]
Soft Switching Dead Time Setting
00=2µs, 01=1.5µs, 10=1µs, 11=0.5µs
b3
SEQ_TBL
Square Wave Sequencer Table Select
0= “PWM-PWM” commutation, 1=“PWM-ON” commutation
b2
SYNCOFF
Synchronous Rectifier (SR) Disable
0=
SR enable, 1=SR disable
External Synchronous Rectifier Configure
0=
SR function control by SYNCOFF bit
b1 EXT_SYN 1=
SR function control by OC_TMR pin
In this selection, the OC_TMR[2:0] bits of CNTL_REG can’t be set to 0, too
OC_TMR pin: HIGH=SR enable, LOW=SR disable
Low-Side Minimum PWM Output Enable. This function is working only on
b0
LPWM
square wave PWM driving
0=
Low side minimum PWM duty output disable
1=
Low side minimum PWM duty output enable
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
FCM8201 • Rev. 1.0.0
16
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