AD5421CREZ-RL7 데이터 시트보기 (PDF) - Analog Devices

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AD5421CREZ-RL7

16-Bit, Serial Input, Loop-Powered, 4 mA to 20 mA DAC

Analog Devices 

Data Sheet

Figure 48 shows a digitally controlled full-scale step and the

resulting filter output. In Figure 48, it can be seen that the peak

amplitude of the filter output signal is less than the required

150 mV, and the transition time is approximately 30 ms.

12

150

10

100

8

50

6

0

4

–50

2

–100

0

–150

–50

–30

–10

10

30

50

TIME (ms)

Figure 48. Digitally Controlled Full-Scale Step and Resulting HART Digital

Filter Output Signal

AD5421

Figure 49 shows the circuit diagram for this measurement. The

47 nF and 168 nF capacitor values for CHART and CSLEW provide

adequate filtering of the digital steps, ensuring that they do not

cause interference.

REGIN

AD5421

LOOP–

CIN COM

VLOOP

RL

168nF

47nF

FROM HART MODEM

Figure 49. Circuit Diagram for Figure 48

Rev. H | Page 25 of 36

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