AD7606-4 데이터 시트보기 (PDF) - Analog Devices
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AD7606-4 Datasheet PDF : 36 Pages
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AD7606/AD7606-6/AD7606-4
TIMING SPECIFICATIONS
AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, VREF = 2.5 V external reference/internal reference, TA = TMIN to TMAX, unless otherwise noted.1
Table 3.
Parameter
PARALLEL/SERIAL/BYTE MODE
tCYCLE
Limit at TMIN, TMAX
Min Typ Max
5
tCONV 2
tWAKE-UP STANDBY
5
9.7
3.45 4
4.15
3
2
7.87
9.1
16.05
18.8
33
39
66
78
133
158
257
315
100
tWAKE-UP SHUTDOWN
Internal Reference
30
External Reference
13
tRESET
50
tOS_SETUP
20
tOS_HOLD
20
t1
40
t2
25
t3
25
t4
0
t5 3
0.5
t6
25
t7
25
PARALLEL/BYTE READ
OPERATION
t8
0
t9
0
t10
16
21
25
32
t11
15
t12
22
Unit Description
1/throughput rate
μs Parallel mode, reading during or after conversion; or serial mode: VDRIVE =
4.75 V to 5.25 V, reading during a conversion using DOUTA and DOUTB lines
μs Serial mode reading during conversion; VDRIVE = 3.3 V
μs
Serial mode reading after a conversion; VDRIVE = 2.3 V, DOUTA and DOUTB lines
Conversion time
μs Oversampling off; AD7606
μs Oversampling off; AD7606-6
μs Oversampling off; AD7606-4
μs Oversampling by 2; AD7606
μs Oversampling by 4; AD7606
μs Oversampling by 8; AD7606
μs Oversampling by 16; AD7606
μs Oversampling by 32; AD7606
μs Oversampling by 64; AD7606
μs STBY rising edge to CONVST x rising edge; power-up time from
standby mode
ms STBY rising edge to CONVST x rising edge; power-up time from
shutdown mode
ms STBY rising edge to CONVST x rising edge; power-up time from
shutdown mode
ns RESET high pulse width
ns BUSY to OS x pin setup time
ns BUSY to OS x pin hold time
ns CONVST x high to BUSY high
ns Minimum CONVST x low pulse
ns Minimum CONVST x high pulse
ns BUSY falling edge to CS falling edge setup time
ms Maximum delay allowed between CONVST A, CONVST B rising edges
ns Maximum time between last CS rising edge and BUSY falling edge
ns Minimum delay between RESET low to CONVST x high
ns CS to RD setup time
ns CS to RD hold time
RD low pulse width
ns
VDRIVE above 4.75 V
ns
VDRIVE above 3.3 V
ns
VDRIVE above 2.7 V
ns
VDRIVE above 2.3 V
ns RD high pulse width
ns CS high pulse width (see Figure 5); CS and RD linked
Rev. 0 | Page 7 of 36
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