LH7A404 데이터 시트보기 (PDF) - NXP Semiconductors.

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LH7A404

32-Bit System-on-Chip

NXP Semiconductors. 

LH7A404

NXP Semiconductors

32-Bit System-on-Chip

ROM

FLASH

SRAM

123

456

789

*0#

GPIO

SDRAM

COMPACT

FLASH

PC

CARD

PCMCIA

DEVICE

HOST

STN/TFT/

AD-TFT

LH7A404

IR

USB

HOST

SSP

UART

SMART

CARD

SCI

TOUCH

SCREEN

CONTR.

MMC/SD

MULTIMEDIA

CARD

DMA

CODEC

AC97

BMI

DC to DC

BATTERY

VOLTAGE

GENERATION

CIRCUITRY

Figure 2. Application Diagram

LH7A404-2

SYSTEM DESCRIPTIONS

ARM922T Processor

The LH7A404 microcontroller features the ARM922T

cached core with an Advanced High-performance Bus

(AHB) interface. The processor is a member of the

ARM9T family of processors. For more information, see

the ARM document, ‘ARM922T Technical Reference

Manual’, available on ARM’s website at www.arm.com.

Clock and State Controller

The clocking scheme in the LH7A404 is based

around two primary oscillator inputs. These are the

14.7456 MHz input crystal and the 32.768 kHz real time

clock oscillator; see Figure 3. The 14.7456 MHz oscil-

lator supplies the main system clock domains for the

LH7A404. The 32.768 kHz oscillator controls the

power-down operations and real time clock peripheral.

The clock and state controller provides the clock gating

and frequency division necessary, and then supplies

the clocks to the processor and rest of the system. The

amount of clock gating that actually takes place

depends on the power saving mode selected.

The 32.768 kHz clock provides the source for the

Real Time Clock tree and power-down logic. This clock

is used for the power state control and is the only clock

in the LH7A404 that runs continuously. The 32.768 kHz

clock is divided down to 1 Hz for the Real Time Clock

counter using a ripple divider to save power.

The 14.7456 MHz source is used to generate the

main system clocks for the LH7A404. It is the source

for PLL1 and PLL2, the primary clock for the peripher-

als, and the source clock to the programmable clock

(PGM) divider.

PLL1 provides the main clock tree for the chip. It gen-

erates the following clocks: FCLK, HCLK, and PCLK.

FCLK is the clock that drives the ARM922T core.

HCLK is the main bus (AHB) clock, as such it clocks

all memory interfaces, bus arbitrators and the AHB

peripherals. HCLK is generated by dividing FCLK by 1,

2, 3, or 4. HCLK can be gated by the system to enable

low power operation.

PCLK is the peripheral bus (APB) clock. It is gener-

ated by dividing HCLK by either 2, 4, or 8.

PLL2 generates a fixed 48 MHz clock signal for the

USB peripheral.

18

Product data sheet

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