P3041NSE7PNC 데이터 시트보기 (PDF) - Freescale Semiconductor
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P3041NSE7PNC Datasheet PDF : 160 Pages
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Hardware Design Considerations
OVDD
From Target
Board Sources
(if any)
HRESET
PORESET
5
10 kΩ
HRESET 4
10 kΩ
PORESET1
1
2
3
4
5
6
22 RESET
7
8
25,26,27,28,
10 kΩ
9
10
31,33,37,38,
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
39,40,43,44,
45,46,49,50,
N/C
51,52,55,56,
57,58,61,62,
63,64,67,68,
69,70
TRST
12
VIO VSense2
2
COP_TMS
6
COP_TDO
10
BA
3
1 kΩ
10 kΩ
10 kΩ
10 kΩ
TRST1
TMS
TDO
33
34
35
36
37
38
COP_TDI
8
COP_TCK
4
TDI
TCK
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
Duplex 70
Connector
Physical Pinout
34
32
20
18
16
14
1
3
7
9
13
15
19
21
5,11,17,23,24,
29,30,35,36,41,
42,47,48,53,54,
Vendor I/O 5 (Aurora HRESET)
Vendor I/O 4 N/C
Vendor I/O 3 N/C
Vendor I/O 2 (Aurora Event Out)
Vendor I/O 1 (Aurora Event In)
Vendor I/O 0 (Aurora HALT)
TX0_P
TX0_N
TX1_P
TX1_N
RX0_P
RX0_N
RX1_P
RX1_N
10 kΩ
EVT[4]
EVT[4]
EVT[1]
EVT[0]
SD_TX09_P
SD_TX09_N
SD_TX08_P
SD_TX08_N
SD_RX09_P
SD_RX09_N
SD_RX08_P
SD_RX08_N
Notes:
59,60,65,66
1. The Aurora port and target board must be able to independently assert PORESET and TRST to the processor
in order to fully control the processor as shown here.
2. Populate this with a 1 kΩ resistor for short-circuit/current-limiting protection.
3.This switch is included as a precaution for BSDL testing. The switch must be closed to position A during BSDL testing
to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch must be closed
to position B.
4. Asserting HRESET causes a hard reset on the device. 5. This is an open-drain gate.
Figure 59. Aurora 70 Pin Connector Duplex Interface Connection
P3041 QorIQ Integrated Processor Hardware Specifications, Rev. 2
150
Freescale Semiconductor
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