MT46V16M8TG-8 데이터 시트보기 (PDF) - Micron Technology

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MT46V16M8TG-8

DOUBLE DATA RATE (DDR) SDRAM

Micron Technology 

NOTES (continued)

39. The voltage levels used are derived from a

minimum VDD level and the referenced test load.

In practice, the voltage levels obtained from a

properly terminated bus will provide signifi-

cantly different voltage values.

40. VIH overshoot: VIH(MAX) = VDDQ+1.5V for a

pulse width ≤ 3ns and the pulse width can not

be greater than 1/3 of the cycle rate. VIL

undershoot: VIL(MIN) = -1.5V for a pulse width ≤

3ns and the pulse width can not be greater than

1/3 of the cycle rate.

41. VDD and VDDQ must track each other.

42. This maximum value is derived from the

referenced test load. In practice, the values

obtained in a typical terminated design may

reflect up to 310ps less for tHZ(MAX) and the

last DVW. tHZ(MAX) will prevail over

tDQSCK(MAX) + tRPST(MAX) condition.

tLZ(MIN) will prevail over tDQSCK(MIN) +

tRPRE(MAX) condition.

43. For slew rates greater than 1V/ns the (LZ)

transition will start about 310ps earlier.

4 4 . During initialization, VDDQ, VTT, and VREF must

be equal to or less than VDD + 0.3V. Alterna-

tively, VTT may be 1.35V maximum during power

up, even if VDD/VDDQ are 0 volts, provided a

minimum of 42 ohms of series resistance is used

between the VTT supply and the input pin.

Figure C

Pull-Down Characteristics

80

70

60

50

40

30

20

10

0

0.0

0.5

1.0

1.5

2.0

2.5

VOUT (V)

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

45. The current Micron part operates below the

slowest JEDEC operating frequency of 83 MHz.

As such, future die may not reflect this option.

4 6 . tRAP ≥ tRCD.

47. For the -75 and -75Z, IDD3N is specified to be

35mA at 100 MHz.

48. Random addressing changing 50% of data

changing at every transfer.

49. Random addressing changing 100% of data

changing at every transfer.

50. CKE must be active (high) during the entire time

a refresh command is executed. That is, from

the time the AUTO REFRESH command is

registered, CKE must be active at each rising clock

edge, until tREF later.

51. IDD2N specifies the DQ, DQS, and DM to be

driven to a valid high or low logic level. IDD2Q

is similar to IDD2F except IDD2Q specifies the

address and control inputs to remain stable.

Although IDD2F, IDD2N, and IDD2Q are

similar, IDD2F is “worst case.”

52. Whenever the operating frequency is altered, not

including jitter, the DLL is required to be reset.

This is followed by 200 clock cycles.

Figure D

Pull-Up Characteristics

0

-20

-40

-60

-80

-100

-120

0.0

0.5

1.0

1.5

2.0

2.5

VDDQ - VOUT (V)

128Mb: x4, x8, x16 DDR SDRAM

128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01

53

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2001, Micron Technology, Inc.

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