A65H73361 데이터 시트보기 (PDF) - AMIC Technology

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A65H73361

128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output

AMIC Technology 

Timing Diagram (Read Write Cycles)

CK

tKHKL

tKLKH

SA

A1

tKHKH

tAVKH

A2

SS

SW

SBW

tSVKH

tKHSX

tKHAX

tKHWX

tWVKH

tWVKH

tKHWX

G

DQ

tKHQZ

Q1

A3

tKHDX

D2

tKHQV

tDVKH

A65H73361/A65H83181 Series

A2

A4

tXHWX

tWVKH

tXHWX

tWVKH

tKHQV

Q3

tKHQX4

tGHQZ

Q2

D4

tDVKH

tKHDX

NOTES:

1.D2 is the input data write in memory location A2.

2.Q2 is output data read from the write buffer, as a result of address A2 being a match from the last write cycle address.

PRELIMINARY (February, 1999, Version 2.0)

11

AMIC Technology, Inc.

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