74ACT74PC(2008) 데이터 시트보기 (PDF) - Fairchild Semiconductor

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74ACT74PC
(Rev.:2008)

Dual D-Type Positive Edge-Triggered Flip-Flop

Fairchild Semiconductor 

Connection Diagram

Logic Symbols

Pin Descriptions

Pin Names

D1, D2

CP1, CP2

CD1, CD2

SD1, SD2

Q1, Q1, Q2, Q2

Description

Data Inputs

Clock Pulse Inputs

Direct Clear Inputs

Direct Set Inputs

Outputs

IEEE/IEC

Truth Table

(Each Half)

Inputs

Outputs

SD

CD

CP

D

Q

Q

L

H

X

X

H

L

H

L

X

X

L

H

L

L

X

X

H

H

H

H

H

H

L

H

H

L

L

H

H

H

L

X

Q0

Q0

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

= LOW-to-HIGH Clock Transition

Q0 (Q0) = Previous Q (Q) before LOW-to-HIGH Transition of Clock

©1988 Fairchild Semiconductor Corporation

74AC74, 74ACT74 Rev. 1.6.1

2

www.fairchildsemi.com

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