74F533PC 데이터 시트보기 (PDF) - Fairchild Semiconductor

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74F533PC

Octal Transparent Latch with 3-STATE Outputs

Fairchild Semiconductor 

Unit Loading/Fan Out

Pin Names

Description

D0–D7

LE

OE

O0–O7

Data Inputs

Latch Enable Input (Active HIGH)

Output Enable Input (Active LOW)

Complementary 3-STATE Outputs

U.L.

HIGH/LOW

1.0/1.0

1.0/1.0

1.0/1.0

150/40 (33.3)

Input IIH/IIL

Output IOH/IOL

20 µA/−0.6 mA

20 µA/−0.6 mA

20 µA/−0.6 mA

−3 mA/24 mA (20 mA)

Function Table

Inputs

LE

OE

D

H

L

H

H

L

L

L

L

X

X

H

X

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Output

O

L

H

O0

Z

Functional Description

The 74F533 contains eight D-type latches with 3-STATE

output buffers. When the Latch Enable (LE) input is HIGH,

data on the Dn inputs enters the latches. In this condition

the latches are transparent, i.e., a latch output will change

state each time its D input changes. When LE is LOW, the

latches store the information that was present on the D

inputs a setup time preceding the HIGH-to-LOW transition

of LE. The 3-STATE buffers are controlled by the Output

Enable (OE) input. When OE is LOW, the buffers are in the

bi-state mode. When OE is HIGH the buffers are in the high

impedance mode but this does not interfere with entering

new data into the latches.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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