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PA7128

Programmable Electrically Erasable Logic Array

International Cmos Technology 

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PA7128 PEELTM Array

Programmable Electrically Erasable Logic Array

Features

s CMOS Electrically Erasable Technology

− Reprogrammable in 28-pin DIP, SOIC and PLCC

packages

2

− As fast as 9ns/15ns (tpdi/tpdx), 83.3MHz (fMAX)

− Industrial grade available for 4.5 to 5.5V Vcc

and -40 to +85 °C temperatures

s Versatile Logic Array Architecture

− 12 I/Os, 14 inputs, 36 registers/latches

− Up to 36 logic cell output functions

− PLA structure with true product-term sharing

− Logic functions and registers can be I/O-buried

s Ideal for Combinatorial, Synchronous and Asyn-

chronous Logic Applications

− Integration of multiple PLDs and random logic

− Buried counters, complex state-machines

− Comparitors, decoders, other wide-gate functions

s Flexible Logic Cell

− Up to 3 output functions per logic cell

− D,T and JK registers with special features

− Independent or global clocks, resets, presets, clock

polarity and output enables

− Sum-of-products logic for output enables

s Development and Programmer Support

− ICT PLACE Development Software

− Fitters for ABEL, CUPL and other software

− Programming support by ICT PDS-3 and other popu-

lar third-party programmers.

s High-Speed Commercial and Industrial Versions

General Description

The PA7128 is a member of the Programmable Electrically

Erasable Logic (PEEL™) Array family based on ICT’s

CMOS EEPROM technology. PEEL™ Arrays free design-

ers from the limitations of ordinary PLDs by providing the

architectural flexibility and speed needed for today’s pro-

grammable logic designs. The PA7128 offers a versatile

logic array architecture with 12 I/O pins, 14 input pins and

36 registers/latches (12 buried logic cells, 12 input regis-

ters/latches, 12 buried I/O registers/latches). Its logic array

implements 50 sum-of-products logic functions that share

64 product terms. The PA7128’s logic and I/O cells (LCCs,

IOCs) are extremely flexible offering up to three output

functions per cell (a total of 36 for all 12 logic cells). Cells

are configurable as D, T and JK registers with independent

or global clocks, resets, presets, clock polarity and other

special features, making the PA7128 suitable for a variety of

combinatorial, synchronous and asynchronous logic appli-

cations. The PA7128 offers pin compatibility and super-set

functionality to popular 28-pin PLDs, such as the 26V12.

Thus, designs that exceed the architectures of such

devices can be expanded upon. The PA7128 supports

speeds as fast as 9ns/15ns (tpdi/tpdx) and 83.3MHz (fMAX)

at moderate power consumption 105mA (75mA typical).

Packaging includes 28-pin DIP, SOIC and PLCC (see Fig-

ure 1). Development and programming support for the

PA7128 is provided by ICT and popular third-party develop-

ment tool manufacturers.

Figure 1. Pin Configuration

Figure 2. Block Diagram

1/CLK1 1

I2

I3

I4

I5

I6

Vcc 7

I8

I9

I 10

I 11

I 12

I 13

I 14

28 1/CLK2

27 I/O

26 I/O

25 I/O

24 I/O

23 I/O

22 I/O

21 GND

20 I/O

19 I/O

18 I/O

17 I/O

16 I/O

15 I/O

DIP

PLCC

1/CLK

1

1

1

1

1

1

Vcc

1

1

1

1

1

1

1

Global Cells

Input Cells

Logic Control Cells

I/O Cells

1CLK2

I/O

I/O

I/O

I/O

I/O

GND

I/O

I/O

I/O

I/O

I/O

I/O

I/O

SOIC

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