AD1833 데이터 시트보기 (PDF) - Analog Devices
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AD1833 Datasheet PDF : 20 Pages
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AD1833
DIGITAL TIMING (Guaranteed over –40؇C to +85؇C, AVDD = DVDD = 5.0 V ؎ 10%)
Min
tDML
MCLK LO Pulsewidth (All Modes)
15
tDMH
MCLK HI Pulsewidth (All Modes)
15
tDBH
BCLK HI Pulsewidth
15
tDBL
BCLK LO Pulsewidth
15
tDLS
LRCLK Setup
5
tDLH
LRCLK Hold (DSP Serial Port Mode Only)
10
tDDS
SDATA Setup
5
tDDH
SDATA Hold
15
tPDRP
PD/RST LO Pulsewidth
10
tCCH
CCLK HI Pulsewidth
10
tCCL
CCLK LO Pulsewidth
10
tCSU
CDATA Setup Time
5
tCHD
CDATA Hold Time
10
tCLH
CLATCH HI Pulsewidth
10
Specifications subject to change without notice.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MCLK INPUT
RESET INPUT
tDMH
tDML
tPDRP
Figure 1. MCLK and RESET Timing
BCLK
L/RCLK
tDBH
tDBL
tDLS
SDATA
LEFT-JUSTIFIED
MODE
SDATA
I2S-JUSTIFIED
MODE
SDATA
RIGHT-JUSTIFIED
MODE
tDDS
MSB
tDDH
MSB-1
tDDS
MSB
tDDH
8-BIT CLOCKS
(24-BIT DATA)
tDDS
MSB
tDDH
12-BIT CLOCKS
(20-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 2. Serial Data Port Timing
–4–
tDDS
LSB
tDDH
REV. 0
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