AD542/AD544/AD547
This particular log ratio circuit is free from the dynamic prob-
lems that plague many other log circuits. The –3 dB bandwidth
is 50 kHz over the top 3 decades, 100 nA to 100 µA, and de-
creases smoothly at lower input levels. This circuit needs no ad-
ditional frequency compensation for stable operation from
input current sources, such as photodiodes, that may have 100
pF of shunt capacitance. For larger input capacitances a 20 pF
integration capacitor around each amplifier will provide a
smoother frequency response.
This log ratio amplifier can be readily adjusted for optimum
accuracy by following this simple procedure. First, apply V1 =
V2 = –10.00 V and adjust “Balance” for VOUT = 0.00 V. Next
apply V1 = –10.00 V, V2 = –1.00 V and adjust gain for VOUT =
+1.00 V. Repeat this procedure until gain and balance readings
are within 2 mV of ideal values.
Figure 34. Differentiator
Figure 35. Low Drift Integrator and
Low Leakage Guarded Reset
Figure 36. Wien-Bridge
Oscillator–fO = 10 kHz
Figure 37. Capacitance
Multiplier
Figure 38. Long Interval
Timer–1,000 Seconds
Figure 39. Positive Peak Detector
–10–
REV. B