AD7190 데이터 시트보기 (PDF) - Analog Devices
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AD7190 Datasheet PDF : 40 Pages
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AD7190
Table 17. Mode Register Bit Designations
Bit Location
Bit Name
Description
MR23 to MR21 MD2 to MD0 Mode select bits. These bits select the operating mode of the AD7190 (see Table 18).
MR20
DAT_STA
This bit enables the transmission of status register contents after each data register read. When
DAT_STA is set, the contents of the status register are transmitted along with each data register read.
This function is useful when several channels are selected because the status register identifies the
channel to which the data register value corresponds.
MR19 to MR18
CLK1 to CLK0
These bits are used to select the clock source for the AD7190. Either the on-chip 4.92 MHz clock or an
external clock can be used. The ability to use an external clock allows several AD7190 devices to be
synchronized. Also, 50 Hz/60 Hz rejection is improved when an accurate external clock drives the
AD7190.
CLK1 CLK0 ADC Clock Source
0
0
External crystal used. The external crystal is connected from MCLK1 to MCLK2.
0
1
External clock used. The external clock is applied to the MCLK2 pin.
1
0
Internal 4.92 MHz clock. Pin MCLK2 is tristated.
1
1
Internal 4.92 MHz clock. The internal clock is available on MCLK2.
MR17 to MR16
These bits must be programmed with a Logic 0 for correct operation.
MR15
SINC3
Sinc3 filter select bit. When this bit is cleared, the sinc4 filter is used (default value). When this bit is set,
the sinc3 filter is used. The benefit of the sinc3 filter compared to the sinc4 filter is its lower settling time
when chop is disabled. For a given output data rate, fADC, the sinc3 filter has a settling time of fADC/3
while the sinc4 filter has a settling time of fADC/4. The sinc4 filter, due to its deeper notches, gives better
50 Hz/60 Hz rejection. At low output data rates, both filters give similar rms noise and similar no
missing codes for a given output data rate. At higher output data rates (FS values less than 5), the sinc4
filter gives better performance than the sinc3 filter for rms noise and no missing codes.
MR14
This bit must be programmed with a Logic 0 for correct operation.
MR13
ENPAR
Enable parity bit. When ENPAR is set, parity checking on the data register is enabled. The DAT_STA bit
in the mode register should be set when the parity check is used. When the DAT_STA bit is set, the
contents of the status register are transmitted along with the data for each data register read.
MR12
This bit must be programmed with a Logic 0 for correct operation.
MR11
Single
Single cycle conversion enable bit. When this bit is set, the AD7190 settles in one conversion cycle so
that it functions as a zero latency ADC. This bit has no affect when multiple analog input channels are
enabled or when the single conversion mode is selected.
MR10
REJ60
This bit enables a notch at 60 Hz when the output data rate is equal to 50 Hz. The bit should only be
set when chop is disabled and when the device is operating with the zero latency function disabled.
This bit allows simultaneous 50 Hz/60 Hz rejection.
MR9 to MR0
FS9 to FS0
Filter output data rate select bits. The 10 bits of data programmed into these bits determine the filter
cutoff frequency, the position of the first notch of the filter, and the output data rate for the part. In
association with the gain selection, it also determines the output noise (and, therefore, the effective
resolution) of the device. When chop is disabled and continuous conversion mode is selected, the first
notch of the filter occurs at a frequency determined by the relationship:
Filter First Notch Frequency = (fMOD/64)/FS
where FS is the decimal equivalent of the code in the FS0 to FS9 bits and is in the range 1 to 1023, and
fmod is the modulator frequency, which is equal to MCLK/16. With a nominal MCLK of 4.92 MHz, this
results in a first notch frequency range from 4.69 Hz to 4.8 kHz.
Changing the filter notch frequency or changing the gain impacts resolution. Table 6 through Table
13 show the effect of the filter notch frequency and gain on the effective resolution of the AD7190.
The output data rate (or effective conversion time) for the device is equal to the frequency selected for
the first notch of the filter. For example, if the first notch of the filter is selected at 50 Hz, a new word is
available at a 50 Hz rate or every 20 ms. When chop is enabled, the output data rate equals
Output Data Rate = (fMOD/64)/(N x FS)
where FS is the decimal equivalent of the code in the FS0 to FS9 bits and is in the range 1 to 1023, and
fmod is the modulator frequency, which is equal to MCLK/16. With a nominal MCLK of 4.92 MHz, this
results in a conversion rate from 4.69/N Hz to 4.8/N kHz, where N is the order of the sinc filter.
Rev. 0 | Page 21 of 40
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