AD7190 데이터 시트보기 (PDF) - Analog Devices

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AD7190

4.8 kHz Ultralow Noise 24-Bit Sigma-Delta ADC with PGA

Analog Devices 

AD7190

Continuous Read

Rather than write to the communications register each time a

conversion is complete to access the data, the AD7190 can be

configured so that the conversions are placed on the DOUT/

RDY line automatically. By writing 01011100 to the commun-

ications register, the user need only apply the appropriate

number of SCLK cycles to the ADC, and the conversion word

is automatically placed on the DOUT/RDY line when a

conversion is complete. The ADC should be configured for

continuous conversion mode.

When DOUT/RDY goes low to indicate the end of a conversion,

sufficient SCLK cycles must be applied to the ADC; the data

conversion is then placed on the DOUT/RDY line. When the

conversion is read, DOUT/RDY returns high until the next

conversion is available. In this mode, the data can be read only

once. Also, the user must ensure that the data-word is read

before the next conversion is complete. If the user has not read

the conversion before the completion of the next conversion,

or if insufficient serial clocks are applied to the AD7190 to

read the word, the serial output register is reset when the next

conversion is complete and the new conversion is placed in

the output serial register.

To exit the continuous read mode, the instruction 01011000

must be written to the communications register while the

RDY pin is low. While in the continuous read mode, the ADC

monitors activity on the DIN line so that it can receive the

instruction to exit the continuous read mode. Additionally, a

reset occurs if 40 consecutive 1s are seen on DIN. Therefore,

DIN should be held low in continuous read mode until an

instruction is to be written to the device.

When several channels are enabled, the ADC continuously

steps through the enabled channels and performs one con-

version on each channel each time that it is selected. DOUT/

RDY pulses low when a conversion is available. When the user

applies sufficient SCLK pulses, the data is automatically placed

on the DOUT/RDY pin. If the DAT_STA bit in the mode

register is set to 1, the contents of the status register are output

along with the conversion. The status register indicates the

channel to which the conversion corresponds.

CS

DIN

DOUT/RDY

SCLK

0x5C

DATA

Figure 31. Continuous Read

DATA

DATA

Rev. 0 | Page 32 of 40

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