AD7393(RevA) 데이터 시트보기 (PDF) - Analog Devices

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AD7393
(Rev.:RevA)

+3 V, Parallel Input Micropower 10- and 12-Bit DACs

Analog Devices 

AD7392/AD7393–SPECIFICATIONS

AD7392 ELECTRICAL CHARACTERISTICS (@ VREF IN = 2.5 V, ؊40؇C < TA < ؉85؇C, unless otherwise noted)

Parameter

Symbol Conditions

3 V ؎ 10% 5 V ؎ 10% Units

STATIC PERFORMANCE

Resolution1

Relative Accuracy2

Differential Nonlinearity2

Zero-Scale Error

Full-Scale Voltage Error

Full-Scale Tempco3

N

INL

DNL

VZSE

VFSE

TCVFS

TA = ϩ25°C

TA = Ϫ40°C, ϩ85°C

TA = ϩ25°C, Monotonic

Monotonic

Data = 000H, TA = ϩ25°C, ϩ85°C

Data = 000H, TA = –40°C

TA = ϩ25°C, ϩ85°C, Data = FFFH

TA = Ϫ40°C, Data = FFFH

12

Ϯ1.8

Ϯ3

Ϯ0.9

Ϯ1

4.0

8.0

Ϯ8

Ϯ20

28

REFERENCE INPUT

VREF IN Range

Input Resistance

Input Capacitance3

VREF

RREF

CREF

0/VDD

2.5

5

ANALOG OUTPUT

Current (Source)

Output Current (Sink)

Capacitive Load3

IOUT

IOUT

CL

Data = 800H, ∆VOUT = 5 LSB

1

Data = 800H, ∆VOUT = 5 LSB

3

No Oscillation

100

LOGIC INPUTS

Logic Input Low Voltage

VIL

Logic Input High Voltage

VIH

Input Leakage Current

IIL

Input Capacitance3

CIL

INTERFACE TIMING3, 5

Chip Select Write Width

tCS

Data Setup

tDS

Data Hold

tDH

Reset Pulsewidth

tRS

0.5

VDDϪ0.6

10

10

45

30

20

40

AC CHARACTERISTICS

Output Slew Rate

Settling Time6

Shutdown Recovery Time

DAC Glitch

Digital Feedthrough

Feedthrough

SR

Data = 000H to FFFH to 000H

0.05

tS

To ± 0.1% of Full Scale

70

tSDR

Q

Code 7FFH to 800H to 7FFH

65

Q

15

VOUT/VREF VREF = 1.5 V dc +1 V p-p,

Data = 000H, f = 100 kHz

–63

SUPPLY CHARACTERISTICS

Power Supply Range

Positive Supply Current

Shutdown Supply Current

Power Dissipation

Power Supply Sensitivity

VDD RANGE

IDD

IDD–SD

PDISS

PSS

DNL < Ϯ1 LSB

VIL = 0 V, No Load

SHDN = 0, VIL = 0 V, No Load

VIL = 0 V, No Load

∆VDD = Ϯ5%

2.7/5.5

55/100

0.1/1.5

300

0.006

NOTES

1One LSB = VREF/4096 V for the 12-bit AD7392.

2The first two codes (000H, 001H) are excluded from the linearity error measurement.

3These parameters are guaranteed by design and not subject to production testing.

4Typicals represent average readings measured at +25 °C.

5All input control signals are specified with tR = tF = 2 ns (10% to 90% of 13 V) and timed from a voltage level of 1.6 V.

6The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.

Specifications subject to change without notice.

12

Ϯ1.8

Ϯ3

Ϯ0.9

Ϯ1

4.0

8.0

Ϯ8

Ϯ20

28

0/VDD

2.5

5

1

3

100

0.8

VDDϪ0.6

10

10

45

15

5

30

0.05

60

80

65

15

–63

2.7/5.5

55/100

0.1/1.5

500

0.006

Bits

LSB max

LSB max

LSB max

LSB max

mV max

mV max

mV max

mV max

ppm/°C typ

V min/max

MΩ typ4

pF typ

mA typ

mA typ

pF typ

V max

V min

µA max

pF max

ns min

ns min

ns min

ns min

V/µs typ

µs typ

µs typ

nV/s typ

nV/s typ

dB typ

V min/max

µA typ/max

µA typ/max

µW max

%/% max

–2–

REV. A

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