AD7999 데이터 시트보기 (PDF) - Analog Devices

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AD7999

4-Channel, 12-/10-/8-Bit ADC with I2C-Compatible Interface in 8-Lead SOT-23

Analog Devices 

THEORY OF OPERATION

The AD7991/AD7995/AD7999 are low power, 12-/10-/8-bit,

single-supply, 4-channel ADCs. Each part can be operated from

a single 2.35 V to 5.5 V supply.

The AD7991/AD7995/AD7999 provide the user with a 4-channel

multiplexer, an on-chip track-and-hold, an ADC, and an I2C-

compatible serial interface, all housed in an 8-lead SOT-23 package

that offers the user considerable space-saving advantages over

alternative solutions.

The AD7991/AD7995/AD7999 normally remains in a power-

down state while not converting. Therefore, when supplies are

first applied, the part is in a power-down state. Power-up is initiated

prior to a conversion, and the device returns to the power-down

state upon completion of the conversion. This automatic power-

down feature allows the device to save power between conversions.

This means any read or write operations across the I2C interface

can occur while the device is in power-down.

CONVERTER OPERATION

The AD7991/AD7995/AD7999 are successive approximation

ADCs built around a capacitive DAC. Figure 18 and Figure 19

show simplified schematics of the ADC during its acquisition

and conversion phases, respectively. Figure 18 shows the ADC

during its acquisition phase: SW2 is closed, SW1 is in Position A,

the comparator is held in a balanced condition, and the sampling

capacitor acquires the signal on VIN. The source driving the

analog input needs to settle the analog input signal to within

one LSB in 0.6 μs, which is equivalent to the duration of the

power-up and acquisition time.

CAPACITIVE

DAC

VIN

AGND

A

SW1

B

SW2

CONTROL

LOGIC

COMPARATOR

Figure 18. ADC Acquisition Phase

AD7991/AD7995/AD7999

When the ADC starts a conversion, as shown in Figure 19, SW2

opens and SW1 moves to Position B, causing the comparator to

become unbalanced. The input is disconnected when the con-

version begins. The control logic and the capacitive DAC are used

to add and subtract fixed amounts of charge from the sampling

capacitor to bring the comparator back into a balanced condition.

When the comparator is rebalanced, the conversion is complete.

The control logic generates the ADC output code. Figure 20 shows

the ADC transfer function.

CAPACITIVE

DAC

A

VIN

SW1

B

SW2

COMPARATOR

CONTROL

LOGIC

AGND

Figure 19. ADC Conversion Phase

ADC Transfer Function

The output coding of the AD7991/AD7995/AD7999 is straight

binary. The designed code transitions occur at successive integer

LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size for

the AD7991/AD7995/AD7999 is VREF/4096, VREF/1024, and

VREF/256, respectively. Figure 20 shows the ideal transfer

characteristics for the AD7991/AD7995/AD7999.

111 ... 111

111 ... 110

111 ... 000

011 ... 111

000 ... 010

000 ... 001

000 ... 000

AD7991 1 LSB = REFIN/4096

AD7995 1 LSB = REFIN/1024

AD7999 1 LSB = REFIN/256

AGND + 1 LSB

+REFIN – 1 LSB

ANALOG INPUT

0V TO REFIN

Figure 20. AD7991/AD7995/AD7999 Transfer Characteristics

Rev. A | Page 17 of 28

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