AD7991/AD7995/AD7999
Parameter
LOGIC INPUTS (SDA, SCL)
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current, IIN
Input Capacitance, CIN6
Input Hysteresis, VHYST
LOGIC OUTPUTS (OPEN DRAIN)
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance6
Output Coding
THROUGHPUT RATE
POWER REQUIREMENTS2
VDD
IDD
ADC Operating, Interface Active
(Fully Operational)
Power-Down, Interface Active7
Power-Down, Interface Inactive7
Power Dissipation
ADC Operating, Interface Active
(Fully Operational)
Power-Down, Interface Active7
Power-Down, Interface Inactive7
Y Version
Min
Typ
Max
Unit
0.7 (VDD)
0.9 (VDD)
0.1 (VDD)
V
V
0.3 (VDD)
V
0.1 (VDD)
V
±1
μA
10
pF
V
0.4
V
0.6
V
±1
μA
10
pF
Straight (natural) binary
18 × (1/fSCL)
17.5 × (1/fSCL)
+ 2 μs
2.7
5.5
V
0.09/0.25 mA
0.25/0.8
mA
0.07/0.16 mA
0.26/0.85 mA
1/1.6
μA
0.3/1.38
mW
0.83/4.4
mW
0.24/0.88 mW
0.86/4.68 mW
3.3/8.8
μW
Test Conditions/Comments
VDD = 2.7 V to 5.5 V
VDD = 2.35 V to 2.7 V
VDD = 2.7 V to 5.5 V
VDD = 2.35 V to 2.7 V
VIN = 0 V or VDD
ISINK = 3 mA
ISINK = 6 mA
fSCL ≤ 1.7 MHz; see the Serial Interface
section
fSCL > 1.7 MHz; see the Serial Interface
section
VREF = VDD; for fSCL = 3.4 MHz,
clock stretching is implemented
Digital inputs = 0 V or VDD
VDD = 3.3 V/5.5 V, 400 kHz fSCL
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL
VDD = 3.3 V/5.5 V, 400 kHz fSCL
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL
VDD = 3.3 V/5.5 V
VDD = 3.3 V/5.5 V, 400 kHz fSCL
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL
VDD = 3.3 V/5.5 V, 400 kHz fSCL
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL
VDD = 3.3 V/5.5 V
1 Functional from VDD = 2.35 V.
2 Sample delay and bit trial delay enabled, t1 = t2 = 0.5/fSCL.
3 For fSCL up to 400 kHz, clock stretching is not implemented. Above fSCL = 400 kHz, clock stretching is implemented.
4 See the Terminology section.
5 For fSCL ≤ 1.7 MHz, clock stretching is not implemented; for fSCL > 1.7 MHz, clock stretching is implemented.
6 Guaranteed by initial characterization.
7 See the Reading from the AD7991/AD7995/AD7999 section.
Rev. A | Page 4 of 28