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AD805BN

Data Retiming Phase-Locked Loop

Analog Devices 

AD805

THEORY OF OPERATION

The AD805 is a delay- and phase- locked loop circuit for clock

recovery and data retiming from an NRZ-encoded data stream.

Figure 8 is a block diagram of the device shown with an external

VCXO. The AD805-VCXO circuit tracks the phase of the input

data using two feedback loops that share a common control

voltage. A high speed delay-locked loop path uses an on-chip

voltage-controlled phase shifter (VCPS) to track the high

frequency components of jitter on the input data. A separate

frequency control loop, using the external VCXO, tracks the low

frequency components of jitter on the input data.

peaking in any regenerative stage can contribute to hazardous

jitter accumulation.

JITTER OUT (dB)

JITTER IN

0 dB

ORDINARY PLL

Y(s)

X(s)

AD805 – VCXO

Z(s)

X(s)

1

sLOW sHIGH

LOG ω

AD805

τ

OBSOLETE DATA

INPUT

VOLTAGE

CONTROLLED

PHASE

SHIFTER

PHASE

DETECTOR

LOOP

FILTER

INTERNAL LOOP

CONTROL VOLTAGE

RETIMING

MODULE

VCXO

(EXTERNAL)

VCXO

CONTROL VOLTAGE

RECOVERED

CLOCK

RETIMED

DATA

Figure 8. AD805-VCXO Clock Recovery Block Diagram

The two loops work together to null out phase error. For

example, when the clock is behind the data, the phase detector

drives the VCXO to a higher frequency and also increases the

delay through the VCPS. These actions serve to reduce the

phase error. The faster clock picks up phase while the delayed

data loses phase. When considering a static phase error, it is

easy to see that since the control voltage is developed by a loop

integrator, the phase error will eventually reduce to zero.

Figure 10. Circuit Jitter Transfer Functions

The error transfer function, e(s)/X(s), has the same high pass

form as an ordinary phase-locked loop. This transfer function is

free to be optimized to give excellent wide-band jitter accommo-

dation since the jitter transfer function, Z(s)/X(s), provides the

narrow-band jitter filtering. The circuit has an error transfer

bandwidth of 3 MHz and a jitter transfer bandwidth of 10 kHz.

The circuit’s two loops contribute to overall jitter accommoda-

tion. At low frequencies, the integrator provides high gain so

that large jitter amplitudes can be tracked with small phase

errors between inputs of the phase detector. In this case, the

VCXO is frequency modulated and jitter is tracked as in an

ordinary phase-locked loop. The amount of low frequency jitter

that can be tracked is a function of the VCXO tuning range. A

wider tuning range corresponds to increased accommodation of

low frequency jitter. The internal loop control voltage remains

Another view of the circuit is that the AD805 VCPS implements

the zero that is required to stabilize a second order phase-locked

small for small phase errors, so the VCPS remains close to the

center of its range, contributing little to jitter accommodation.

loop and that the zero is placed in the feedback path so it does

At medium jitter frequencies, the gain and tuning range of the

not appear in the closed-loop transfer function. Jitter peaking in VCXO are not enough to track input jitter. In this case the

an ordinary second order phase-locked loop is caused by the VCXO control voltage input starts to hit the rails of its maxi-

presence of this zero in the closed-loop transfer function. Since mum voltage swing and the VCXO frequency output spends

the AD805-VCXO circuit is free of any zero in its closed-loop

most of the time at one or the other extreme of its tuning range.

transfer function, the circuit is free of jitter peaking.

The size of the VCXO tuning range therefore has a small effect

A linearized block diagram of the AD805-VCXO circuit is

shown in Figure 9. The two loops simultaneously provide wide-

band jitter accommodation and narrow-band jitter filtering.

on the jitter accommodation. The AD805 internal loop control

voltage is now larger, so the VCPS takes on the burden of

tracking input jitter. The VCPS range (in UI) is seen as the

plateau on the jitter tolerance curve (Figure 11). The VCPS has

Y

a minimum range of 2 UI.

τ

100

e

X+– +

∑

∑

K

1

s

PHASE

–

INT

1

Z

s

VCO

SHIFTER

PHASE

10

DETECTOR

Z(s)

X(s) =

s2

1

+ τs + 1

K

e(s)

X(s)

=

s2

s2+ Kτs + K

Figure 9. AD805-VCXO Circuit Linearized Block Diagram

The jitter transfer function, Z(s)/X(s), is second order and low

pass, providing excellent filtering. Note that the jitter transfer

function has no zero, unlike ordinary second-order phase-locked

loops. This means that the circuit has fundamentally no jitter

peaking (see Figure 10). Having no jitter peaking makes this

circuit ideal for signal regeneration applications where jitter

AD805-VCXO

JITTER TOLERANCE

1

CCITT TYPE A MASK

0.1

0.1

1

10

100

1000

10000

FREQUENCY – kHz

Figure 11. Jitter Accommodation Design Limit

–6–

REV. 0

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