AD9279
TABLE OF CONTENTS
Features .............................................................................................. 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Specifications.......................................................................... 3
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 7
ADC Timing Diagrams ............................................................... 8
Absolute Maximum Ratings............................................................ 9
Thermal Impedance ..................................................................... 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 13
TGC Mode................................................................................... 13
CW Doppler Mode..................................................................... 16
REVISION HISTORY
10/10—Revision 0: Initial Version
Equivalent Circuits......................................................................... 17
Ultrasound Theory of Operation ................................................. 19
Channel Overview.......................................................................... 20
TGC Operation........................................................................... 20
CW Doppler Operation............................................................. 33
Serial Port Interface (SPI).............................................................. 37
Hardware Interface..................................................................... 37
Memory Map .................................................................................. 39
Reading the Memory Map Table.............................................. 39
Reserved Locations .................................................................... 39
Default Values ............................................................................. 39
Logic Levels................................................................................. 39
Outline Dimensions ....................................................................... 43
Ordering Guide .......................................................................... 43
Rev. 0 | Page 2 of 44