AD9516-1/PCBZ(Rev0) 데이터 시트보기 (PDF) - Analog Devices
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AD9516-1/PCBZ Datasheet PDF : 84 Pages
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Parameter
PHASE/FREQUENCY DETECTOR (PFD)
PFD Input Frequency
Antibacklash Pulse Width
CHARGE PUMP (CP)
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
CPRSET Range
ICP High Impedance Mode Leakage
Sink-and-Source Current Matching
ICP vs. CPV
ICP vs. Temperature
PRESCALER (PART OF N DIVIDER)
Prescaler Input Frequency
P = 1 FD
P = 2 FD
P = 3 FD
P = 2 DM (2/3)
P = 4 DM (4/5)
P = 8 DM (8/9)
P = 16 DM (16/17)
P = 32 DM (32/33)
Prescaler Output Frequency
PLL DIVIDER DELAYS
000
001
010
011
100
101
110
111
NOISE CHARACTERISTICS
In-Band Phase Noise of the Charge
Pump/Phase Frequency Detector
(In-Band Means Within the LBW
of the PLL)
@ 500 kHz PFD Frequency
@ 1 MHz PFD Frequency
@ 10 MHz PFD Frequency
@ 50 MHz PFD Frequency
PLL Figure of Merit (FOM)
Min Typ Max
100
45
1.3
2.9
6.0
4.8
0.60
2.5
2.7/10
1
2
1.5
2
AD9516-1
Unit Test Conditions/Comments
MHz Antibacklash pulse width = 1.3 ns, 2.9 ns
MHz Antibacklash pulse width = 6.0 ns
ns
0x17<1:0> = 01b
ns
0x17<1:0> = 00b; 0x17<1:0> = 11b
ns
0x17<1:0> = 10b
Programmable
mA
With CPRSET = 5.1 kΩ
mA
%
CPV = VCP/2
kΩ
nA
%
0.5 < CPV < VCP − 0.5 V
%
0.5 < CPV < VCP − 0.5 V
%
CPV = VCP/2 V
300
600
900
600
1000
2400
3000
3000
300
Off
330
440
550
660
770
880
990
−165
−162
−151
−143
−220
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz A, B counter input frequency (prescaler
input frequency divided by P)
Register 0x19: R <5:3>, N <2:0>; see Table 53
ps
ps
ps
ps
ps
ps
ps
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
The PLL in-band phase noise floor is estimated
by measuring the in-band phase noise at the
output of the VCO and subtracting 20log(N)
(where N is the value of the N divider)
Reference slew rate > 0.25 V/ns. FOM +10log (fPFD)
is an approximation of the PFD/CP in-band
phase noise (in the flat region) inside the PLL
loop bandwidth. When running closed loop,
the phase noise, as observed at the VCO output,
is increased by 20log(N)
Rev. 0 | Page 5 of 84
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