AD9549 데이터 시트보기 (PDF) - Analog Devices

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AD9549

Dual Input Network Clock Generator/Synchronizer

Analog Devices 

AD9549

2.0

1.5

1.0

0.5

0

10

30

50

70

90

SYSTEM CLOCK PLL INPUT FREQUENCY (MHz)

Figure 9. 12 kHz to 20 MHz RMS Jitter vs. System Clock PLL Input Frequency,

SYSCLK = 1 GHz, fREF = 19.44 MHz, fOUT = 155.52 MHz

–70

RMS JITTER (12kHz TO 20MHz): 1.26ps

–80

RMS JITTER (50kHz TO 80MHz): 1.30ps

–90

–100

–110

–120

–130

–140

–150

10

100

1k

10k 100k 1M

10M 100M

FREQUENCY OFFSET (Hz)

Figure 10. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz

(SYSCLK PLL Enabled and Driven by a 25 MHz Fox Crystal Oscillator),

fREF = 19.44 MHz, fOUT = 155.52 MHz, DPLL Loop BW = 1 kHz

–70

RMS JITTER (12kHz TO 20MHz): 4.2ps

–80

–90

–100

–110

–120

–130

–140

–150

10

100

1k

10k

100k

1M

10M

FREQUENCY OFFSET (Hz)

Figure 11. Additive Phase Noise at HSTL Output Driver, SYSCLK = 500 MHz

(SYSCLK PLL Disabled), fREF = 10.24 MHz, fOUT = 20.48 MHz,

DPLL Loop BW = 1 kHz

Rev. D | Page 14 of 76

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