AD9549 데이터 시트보기 (PDF) - Analog Devices
부품명
상세내역
제조사
AD9549 Datasheet PDF : 76 Pages
| |||
Parameter
SYSTEM CLOCK INPUT
Min
Typ
Max
SYSCLK PLL Bypassed
Input Capacitance
Input Resistance
Internally Generated DC Bias Voltage2
Differential Input Voltage Swing3
SYSCLK PLL Enabled
Input Capacitance
Input Resistance
Internally Generated DC Bias Voltage2
Differential Input Voltage Swing3
Crystal Resonator with SYSCLK PLL Enabled
Motional Resistance
CLOCK OUTPUT DRIVERS
HSTL Output Driver
Differential Output Voltage Swing
2.4
0.93
632
2.4
0.93
632
1080
1.5
2.6
1.17
3
2.6
1.17
9
1280
2.8
1.38
2.8
1.38
100
1480
Common-Mode Output Voltage2
CMOS Output Driver
0.7
0.88
1.06
Output Voltage High (VOH)
Output Voltage Low (VOL)
Output Voltage High (VOH)
Output Voltage Low (VOL)
TOTAL POWER DISSIPATION
All Blocks Running4
Power-Down Mode
2.7
0.4
1.4
0.4
1060
24
1310
70
Digital Power-Down Mode
Default with SYSCLK PLL Enabled
565
713
955
Default with SYSCLK PLL Disabled
945
1115
With REFA or REFB Power-Down
With HSTL Clock Driver Power-Down
With CMOS Clock Driver Power-Down
1 Must be ≤0 V relative to AVDD3 (Pin 14) and ≥0 V relative to AVSS (Pin 33, Pin 43).
2 Relative to AVSS (Pin 33, Pin 43).
3 Must be ≤0 V relative to AVDD (Pin 36) and ≥0 V relative to AVSS (Pin 33, Pin 43).
4 Typical measurement done with only REFA and HSTL output doubler turned off.
1105
1095
1107
AD9549
Unit
Test Conditions/Comments
System clock inputs should always be ac-
coupled (both single-ended and differential)
pF
kΩ
V
mV p-p
Single-ended, each pin
Differential
0 dBm into 50 Ω
pF
kΩ
V
mV p-p
Single-ended, each pin
Differential
0 dBm into 50 Ω
Ω
25 MHz, 3.2 mm × 2.5 mm AT cut
mV
Output driver static; see Figure 12 for output
swing vs. frequency
V
Output driver static; see Figure 13 and
Figure 14 for output swing vs. frequency
V
IOH = 1 mA, (Pin 37) = 3.3 V
V
IOL = 1 mA, (Pin 37) = 3.3 V
V
IOH = 1 mA, (Pin 37) = 1.8 V
V
IOL = 1 mA, (Pin 37) = 1.8 V
mW
Worst case over supply, temperature, process
mW
Using either the power-down and enable
register (Register 0x0010) or the PWRDOWN pin
mW
mW
After reset or power-up with fS = 1 GHz,
S4 = 0, S1 to S3 = 1, fSYSCLK = 25 MHz
mW
After reset or power-up with fS = 1 GHz,
S1 to S4 = 1
mW
One reference still powered up
mW
mW
Rev. D | Page 5 of 76
Share Link: 