AD9575ARUZLVD 데이터 시트보기 (PDF) - Analog Devices

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AD9575ARUZLVD

Network Clock Generator, Two Outputs

Analog Devices 

AD9575

–110

–115

–120

–125

–130

–135

–140

–145

–150

–155

–160

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 11. Phase Noise at LVPECL, 161.13 MHz Clock Output

–110

–115

–120

–125

–130

–135

–140

–145

–150

–155

–160

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 12. Phase Noise at LVPECL, 312.5 MHz Clock Output

140

130

LVPECL

120

110

LVDS

100

90

80

1

2

3

4

5

6

7

8

MODE

Figure 13. Typical Supply Current vs. Mode (see Table 12)

M2

M2 50mV 2ns

M3 50mV 2ns

Figure 14. 156.25 MHz LVDS Output

M2

M2 100mV 1ns

M3 100mV 1ns

Figure 15. 312.5 MHz LVPECL Output

M2

M2 100mV 10ns

M3 100mV 10ns

Figure 16. 62.5 MHz LVCMOS Output

Rev. A | Page 10 of 16

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