ADG412(RevA) 데이터 시트보기 (PDF) - Analog Devices
부품명
상세내역
제조사
ADG412 Datasheet PDF : 8 Pages
| |||
ADG411/ADG412/ADG413
120
VDD = +15V
VSS = –15V
VL = +5V
100
80
60
40
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
Figure 7. Off Isolation vs. Frequency
110
VDD = +15V
VSS = –15V
100
VL = +5V
90
80
70
60
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
Figure 8. Crosstalk vs. Frequency
APPLICATION
Figure 9 illustrates a precise, fast, sample-and-hold circuit. An
AD845 is used as the input buffer while the output operational
amplifier is an AD711. During the track mode, SW1 is closed
and the output VOUT follows the input signal VIN. In the hold
mode, SW1 is opened and the signal is held by the hold capaci-
tor CH.
Due to switch and capacitor leakage, the voltage on the hold
capacitor will decrease with time. The ADG411/ADG412/
ADG413 minimizes this droop due to its low leakage specifica-
tions. The droop rate is further minimized by the use of a poly-
styrene hold capacitor. The droop rate for the circuit shown is
typically 30 µV/µs.
A second switch, SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differen-
tial effect on the op amp AD711, which will minimize charge
injection effects. Pedestal error is also reduced by the compensa-
tion network RC and CC. This compensation network also re-
duces the hold time glitch while optimizing the acquisition time.
Using the illustrated op amps and component values, the pedes-
tal error has a maximum value of 5 mV over the ± 10 V input
range. Both the acquisition and settling times are 850 ns.
+15V
VIN
AD845
–15V
+15V +5V
SW1
S
D
SW2
S
D
ADG411
ADG412
ADG413
2200pF
+15V
RC
75⍀
CC
1000pF
CH
2200pF
AD711
–15V
VOUT
–15V
Figure 9. Fast, Accurate Sample-and-Hold
–6–
REV. A
Share Link: 