ADG622 데이터 시트보기 (PDF) - Analog Devices

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ADG622

CMOS ±5 V/+5 V, 4 Ω Dual SPST Switches

Analog Devices 

ADG621/ADG622/ADG623

TEST CIRCUITS

IDS

V1

S

D

VS

RON = V1/IDS

Figure 16. On Resistance

IS (OFF)

A

S

VS

ID (OFF)

D

A

VD

Figure 17. Off Leakage

S

NC

ID (ON)

DA

VD

NC = NO CONNECT

Figure 18. On Leakage

VDD

0.1µF

VSS

0.1µF

VDD VSS

S

D

VOUT

VS

IN

RL

300Ω

CL

35pF

GND

ADG621 50%

VIN

VIN

ADG622 50%

VOUT

90%

tON

50%

50%

90%

tOFF

Figure 19. Switching Times (tON, tOFF)

VDD VSS

0.1µF

0.1µF

S1

VS1

S2

VS2

IN1, IN2

VDD VSS

VIN

GND

D1

D2

RL2

300Ω

VOUT2

CL2

35pF

RL1

300Ω

VOUT1

CL1

35pF

VIN 0V

VOUT1 0V

50%

90%

VOUT2

90%

0V

tBBM

Figure 20. Break-Before-Make Time Delay, tBBM (ADG623 Only)

50%

90%

90%

tBBM

RS

VS

VDD

VSS

VDD

VSS

S

D

IN

GND

SW ON

VOUT

CL

1nF

VIN

VOUT

SW OFF

QINJ = CL × ΔVOUT

ΔVOUT

Figure 21. Charge Injection

Rev. B | Page 10 of 12

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