ADG633YCPZ(RevB) 데이터 시트보기 (PDF) - Analog Devices
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ADG633YCPZ Datasheet PDF : 16 Pages
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ADG633
Data Sheet
SINGLE-SUPPLY OPERATION
VDD = 5 V, VSS = 0 V, GND = 0 V, TA = −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match
Between Channels, ΔRON
On-Resistance Flatness, RFLAT(ON)
LEAKAGE CURRENTS
Source Off Leakage, IS(OFF)
Drain Off Leakage, ID(OFF)
Channel On Leakage, ID(ON), IS(ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
+25°C
85
150
4.5
8
13
±0.005
±0.2
±0.005
±0.2
±0.005
±0.2
0.005
Digital Input Capacitance, CIN
2
DYNAMIC CHARACTERISTICS1
tTRANSITION
100
150
tON (EN)
100
150
tOFF (EN)
25
35
Break-Before-Make Time Delay, tBBM 90
Charge Injection
0.5
1
Off Isolation
−90
Channel-to-Channel Crosstalk
−90
−3 dB Bandwidth
520
CS(OFF)
5
CD(OFF)
8
CD(ON), CS(ON)
12
POWER REQUIREMENTS2
IDD
0.01
−40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
0 to VDD
V
VDD = 4.5 V, VSS = 0 V
Ω typ
VS = 0 V to 4.5 V, IS = 1 mA; see Figure 20
160
200
Ω max VS = 0 V to 4.5 V, IS = 1 mA; see Figure 20
Ω typ
VS = +3.5 V, IS = 1 mA
9
10
Ω max VS = +3.5 V, IS = 1 mA
14
16
Ω typ
VDD = 5 V, VSS = 0 V, VS = 1.5 V to 4 V, IS = 1 mA
VDD = 5.5 V
nA typ VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 21
±5
nA max VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 21
nA typ VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 22
±5
nA max VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 22
nA typ VS = VD = 1 V or 4.5 V; see Figure 23
±5
nA max VS = VD = 1 V or 4.5 V; see Figure 23
2.4
V min
0.8
V max
μA typ
VIN = VINL or VINH
±1
μA max VIN = VINL or VINH
pF typ
ns typ
RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 24
190
220
ns max RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 24
ns typ
RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26
190
220
ns max RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26
ns typ
RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26
45
50
ns max RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26
ns typ
RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3 V; see Figure 25
10
ns min RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3 V; see Figure 25
pC typ VS = 2.5 V, RS = 0 Ω, CL = 1 nF; see Figure 27
pC max VS = 2.5 V, RS = 0 Ω, CL = 1 nF; see Figure 27
dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 30
MHz typ RL = 50 Ω, CL = 5 pF; see Figure 29
pF typ f = 1 MHz
pF typ f = 1 MHz
pF typ f = 1 MHz
μA typ
VDD = 5.5 V
Digital inputs = 0 V or 5.5 V
1
μA max Digital inputs = 0 V or 5.5 V
1 Guaranteed by design; not subject to production test.
2 The device is fully specified at a ±5 V dual supply and at 5 V and 3.3 V single supplies. It is possible to operate the ADG633 with unbalanced supplies or at other voltage
supplies ( ±2 V to ±6 V, and 2 V to 12 V); however, the switch characteristics change. These changes include, but are not limited to: analog signal range, on resistance,
leakage, VINL, VINH, and switching times. The optimal power-up sequence for the device is: ground, VDD, VSS, and then the digital inputs, before applying the analog input
signal.
Rev. B | Page 4 of 16
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