ADMCF326 데이터 시트보기 (PDF) - Analog Devices
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ADMCF326 Datasheet PDF : 36 Pages
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ADMCF326
over half the PWM period. The switching signals produced by
the three-phase timing unit are also adjusted to incorporate the
programmed dead time value in the PWMDT Register.
The PWM is center-based. This means that in Single Update Mode
the resulting output waveforms are symmetrical and centered in
the PWMSYNC period. Figure 7 presents a typical PWM tim-
ing diagram illustrating the PWM-related registers’ (PWMCHA,
PWMTM, PWMDT, and PWMSYNCWT) control over the
waveform timing in both half cycles of the PWM period. The
magnitude of each parameter in the timing diagram is determined
by multiplying the integer value in each register by tCK (typically
50 ns). It may be seen in the timing diagram how dead time is
incorporated into the waveforms by moving the switching edges
away from the instants set by the PWMCHA Register.
PWMCHA PWMCHA
AH
2 ؋ PWMDT
AL
PWMSYNC
2 ؋ PWMDT
PWMSYNCWT + 1
SYSSTAT (3)
PWMTM
PWMTM
Figure 7. Typical PWM Outputs of Three-Phase Timing
Unit in Single Update Mode
Each switching edge is moved by an equal amount (PWMDT
× tCK) to preserve the symmetrical output patterns. The PWMSYNC
pulse, whose width is set by the PWMSYNCWT Register, is also
shown. Bit 3 of the SYSSTAT Register indicates which half cycle
is active. This can be useful in Double Update Mode, as will be
discussed later.
The resultant on-times of the PWM signals shown in Figure 7
may be written as:
TAH = 2 × (PWMCHA – PWMDT ) × tCK
TAL = 2 × (PWMTM – PWMCHA – PWMDT ) × tCK
The corresponding duty cycles are:
d AH
= TAH
TS
=
PWMCHA – PWMDT
PWMTM
d AL
=
TAL
TS
=
PWMTM
–
PWMCHA –
PWMTM
PWMDT
Obviously, negative values of TAH and TAL are not permitted
because the minimum permissible value is zero, corresponding
to a 0% duty cycle. In a similar fashion, the maximum value is
TS, corresponding to a 100% duty cycle.
The output signals from the timing unit for operation in Double
Update Mode are shown in Figure 8. This illustrates a completely
general case where the switching frequency, dead time, and duty
cycle are all changed in the second half of the PWM period. Of
course, the same value for any or all of these quantities could be
used in both halves of the PWM cycle. However, it can be seen
that there is no guarantee that symmetrical PWM signals will
be produced by the timing unit in this Double Update Mode.
Additionally, it is seen that the dead time is inserted into the
PWM signals in the same way as in the Single Update Mode.
PWMCHA1 PWMCHA2
AH
AL
PWMSYNC
2 ؋ PWMDT1
PWMSYNCWT1 + 1
2 ؋ PWMDT2
PWMSYNCWT2 + 1
SYSSTAT (3)
PWMTM1
PWMTM2
Figure 8. Typical PWM Outputs of Three-Phase Timing
Unit in Double Update Mode
In general, the on-times of the PWM signals in Double Update
Mode are defined by:
( ) TAH = PWMCHA1 + PWMCHA2 − PWMDT1 − PWMDT2 × tCK
T AL
=
PWMTM1 +
PWMCHA2
PWMTM2 − PWMCHA1
− PWMDT1 − PWMDT2
−
× tCK
where the subscript 1 refers to the value of that register during
the first half cycle and the subscript 2 refers to the value during
the second half cycle. The corresponding duty cycles are:
d AH
= TAH
TS
= PWMCHA1 + PWMCHA2
PWMTM1 + PWMTM2
− PWMDT1 + PWMDT2
PWMTM1 + PWMTM2
d AL
=
TAL
TS
( ) = PWMTM1 + PWMTM2 + PWMCHA1
PWMTM1 + PWMTM2
( ) PWMCHA2 + PWMDT1 + PWMDT2
–
PWMTM1 + PWMTM2
because for the completely general case in Double Update Mode,
the switching period is given by:
( ) TS = PWMTM1 + PWMTM2 × tCK
Again, the values of TAH and TAL are constrained to lie between
zero and TS.
PWM signals similar to those illustrated in Figure 7 and Figure 8
can be produced on the BH, BL, CH, and CL outputs by pro-
gramming the PWMCHB and PWMCHC Registers in a manner
identical to that described for PWMCHA.
The PWM controller does not produce any PWM outputs until
all of the PWMTM, PWMCHA, PWMCHB, and PWMCHC
Registers have been written to at least once. After these registers
have been written, the counters in the three-phase timing unit
–14–
REV. B
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