ADMCF326 데이터 시트보기 (PDF) - Analog Devices

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ADMCF326

28-Lead Flash Memory DSP Motor Controller

Analog Devices 

ADMCF326

Table V. Fundamental Characteristics of PWM Generation Unit of ADMCF326

16-BIT PWM TIMER

Parameter

Counter Resolution

Edge Resolution (Single Update Mode)

Edge Resolution (Double Update Mode)

Programmable Dead Time Range

Programmable Dead Time Increments

Programmable Pulse Deletion Range

Programmable Pulse Deletion Increments

PWM Frequency Range

PWMSYNC Pulsewidth (TCRST)

Gate Drive Chop Frequency Range

Min

Typ

16

100

50

0

100

0

100

150

0.05

0.02

Max

100

100

12.5

5

Unit

Bits

ns

ns

µs

ns

µs

ns

Hz

µs

MHz

Restarting the PWM after a fault condition is detected requires

clearing the fault and reinitializing the PWM. Clearing the fault

requires that PWMTRIP returns to a HI state. After the fault has

been cleared, the PWM can be restarted by writing to registers

PWMTM, PWMCHA, PWMCHB, and PWMCHC. After the fault

is cleared and the PWM registers are initialized, internal timing of

the three-phase timing unit will resume, and the new duty cycle

values will be latched on the next rising edge of PWMSYNC.

PWM Registers

The configuration of the PWM registers is described at the end

of the data sheet. The parameters of the PWM block are tabu-

lated in Table V.

ADC OVERVIEW

The ADC of the ADMCF326 is based upon the single slope

conversion technique. This approach offers an inherently

monotonic conversion process within the noise and stability of its

components, and there will be no missing codes.

Table VI. ADC Auxiliary Channel Selection

Select

VAUX0

VAUX1

VAUX2

Calibration (VREF)

MODECTRL (1)

ADCMUX1

0

0

1

1

MODECTRL (0)

ADCMUX0

0

1

0

1

The single slope technique has been adapted on the ADMCF326

for four channels that are simultaneously converted. Refer to

Figure 11 for the functional schematic of the ADC. Three of

the main inputs (V1, V2, and V3) are directly connected as

high impedance voltage inputs. The fourth channel has been con-

figured with a serially-connected 4-to-1 multiplexer. Table VI

shows the multiplexer input selection codes. One of these auxil-

iary multiplexed channels is used to calibrate the ramp against the

internal voltage reference (VREF).

ICONST

C EXTERNAL

CHARGING

CAP

GND

V1

V2

V3

VAUX0

VAUX1

VAUX2

VC

ICONST_TRIM<2:0>

(CAP RESET)

PWMSYNC (CONVST)

CLK MODECTRL<7>

ADC

REGISTERS

COMP

V1L

COMP

COMP

V2L

12-BIT

ADC

TIMER

BLOCK

V3L

COMP VAUXL

4–1

MUX

ADC REGISTERS

ADC1

ADC2

ADC3

ADCAUX

MODECTRL<0..1>

VREF

Figure 11. ADC Overview

Comparing each ADC input to a reference ramp voltage and

timing the comparison of the two signals performs the conversion

process. The actual conversion point is the time point inter-

section of the input voltage and the ramp voltage (VC) as shown in

Figure 12. This time is converted to counts by the 12-bit ADC

Timer Block and is stored in the ADC registers. The ramp voltage

used to perform the conversion is generated by driving a fixed

current into an off-chip capacitor, where the capacitor voltage is

VC = (I C ) × t

Following reset, VC = 0 at t = 0. This reset and the start of

the conversion process are initiated by the PWMSYNC pulse,

as shown in Figure 12. The width of the PWMSYNC pulse is

controlled by the PWMSYNCWT Register and should be pro-

grammed according to Figure 13 to ensure complete resetting.

In order to compensate for IC process manufacturing tolerances

(and to adjust for capacitor tolerances), the current source of the

ADMCF326 is software programmable. The software setting of the

magnitude of the ICONST current generator is accomplished by

selecting one of eight steps over approximately 20% current range.

REV. B

–17–

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