ADMCF326 데이터 시트보기 (PDF) - Analog Devices
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ADMCF326 Datasheet PDF : 36 Pages
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ADMCF326
ADC Reference Ramp Calibration
The peak of the ADC ramp voltage should be as close as possible
to 3.5 V to achieve the optimum ADC resolution and signal range.
When the current source is in the default state, the peak of the
ADC ramp slope will be lower than this “3.5 V” target ramp.
When the current source value is increased, the ADC ramp
slope will become closer to the target value. The “tuned” ramp
slope is the one closest to the target ramp.
A simple calibration procedure using the internal 2.5 V reference
voltage allows the selection of the ICONST_TRIM Register
value to reach this:
1. A high quality linear ADC capacitor is selected using Figure 14
for a tuned ICONST.
2. Program PWMSYNCWT to proper count as in Figure 13.
3. The ADC Max Count is calculated, as described in a previ-
ous section.
4. The target reference conversion is calculated as TARGET =
(Max Count) × (2.5 V/3.5 V).
5. Reset or software sets the ICONST_TRIM Register to zero.
6. Select calibration channel in software on ADC multiplexer.
7. The calibration channel value is compared with the target
reference conversion.
8. If this value is greater than the TARGET, the ICONST_TRIM
value is incremented by one, and Step 7 is repeated.
9. If the calibration channel value is less than the TARGET,
the calibration is completed.
3.5V
VREF
TARGET
RAMP
MINIMUM
RAMP
The auxiliary PWM system of the ADMCF326 can operate in two
different modes: Independent mode or Offset mode. The operating
mode of the auxiliary PWM system is controlled by Bit 8 of the
MODECTRL Register. Setting Bit 8 of the MODECTRL Register
places the auxiliary PWM system in the Independent Mode. In
this mode, the two auxiliary PWM generators are completely
independent, and separate switching frequencies and duty cycles
may be programmed for each auxiliary PWM output. In this mode,
the 8-bit AUXTM0 Register sets the switching frequency of the
signal at the AUX0 output pin. Similarly, the 8-bit AUXTM1
Register sets the switching frequency of the signal at the AUX1 pin.
The fundamental time increment for the auxiliary PWM outputs
is twice the DSP instruction rate (or 2 tCK) and the correspond-
ing switching periods are given by:
( ) TAUX 0 = 2 × AUXTM 0 + 1 × tCK
( ) TAUX 1 = 2 × AUXTM1 + 1 × tCK
Since the values in both AUXTM0 and AUXTM1 can range from
0 to 0xFF, the achievable switching frequency of the auxiliary PWM
signals may range from 39.1 kHz to 10 MHz for a CLKOUT
frequency of 20 MHz.
The on-time of the two auxiliary PWM signals is programmed
by the two 8-bit AUXCH0 and AUXCH1 Registers, according to:
( ) TON ,AUX 0 = 2 × AUXTM 0 × tCK
( ) TON ,AUX 1 = 2 × AUXTM 1 × tCK
so that output duty cycles from 0% to 100% are possible. Duty
cycles of 100% are produced if the on-time value exceeds the
period value. Typical auxiliary PWM waveforms in Independent
Mode are shown in Figure 16(a).
When Bit 8 of the MODECTRL Register is cleared, the auxil-
iary PWM channels are placed in Offset Mode. In Offset Mode,
the switching frequencies of the two signals on the AUX0 and
AUX1 pins are identical and controlled by AUXTM0 in a man-
ner similar to that previously described for Independent Mode.
In addition, the on times of both the AUX0 and AUX1 signals
are controlled by the AUXCH0 and AUXCH1 Registers as be-
fore. However, in this mode the AUXTM1 Register defines the
offset time from the rising edge of the signal on the AUX0 pin
to that on the AUX1 pin according to:
0.3V
Figure 15. Current Ramp
ADC Registers
The configuration of all registers of the ADC System is shown at
the end of the data sheet.
AUXILIARY PWM TIMERS
Overview
The ADMCF326 provides two variable frequency, variable duty
cycle, 8-bit, auxiliary PWM outputs that are available at the AUX1
and AUX0 pins when enabled. These auxiliary PWM outputs
can be used to provide switching signals to other circuits in a
typical motor control system such as power factor corrected
front end converters or other switching power converters. Alter-
natively, by addition of a suitable filter network, the auxiliary
PWM output signals can be used as simple single-bit digital-to-
analog converters.
( ) TOFFSET = 2 × AUXTM 1 + 1 × tCK
For correct operation in this mode, the value written to the
AUXTM1 Register must be less than the value written to the
AUXTM0 Register. Typical auxiliary PWM waveforms in Offset
Mode are shown in Figure 16(b). Again, duty cycles from 0% to
100% are possible in this mode.
In both operating modes, the resolution of the auxiliary PWM
system is eight bits only at the minimum switching frequency
(AUXTM0 = AUXTM1 = 255 in Independent Mode, AUXTM0
= 255 in offset mode). Obviously, as the switching frequency is
increased, the resolution is reduced.
Values can be written to the auxiliary PWM registers at any
time. However, new duty cycle values written to the AUXCH0
and AUXCH1 Registers only become effective at the start of the
next cycle. Writing to the AUXTM0 or AUXTM1 Registers
causes the internal timers to be reset to 0 and new PWM cycles
to begin.
REV. B
–19–
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