ADP1051 데이터 시트보기 (PDF) - Analog Devices
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ADP1051 Datasheet PDF : 108 Pages
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Data Sheet
ADP1051
The averaging period of the CS1 current and the speed of the dead
time adjustment can also be programmed in Register 0xFE66 to
accommodate faster or slower adjustment.
The light load mode digital compensator is also used during light
load mode and deep light load mode.
NORMAL MODE
For example, if the ADTC threshold is set to 0.8 A, tR1 has a
nominal rising edge of 100 ns. If the ADTC offset setting for tR1
is 100 ns at a CS1 current of 0 A, tR1 moves to 200 ns when the CS1
current is 0 A and to 150 ns when the CS1 current is 0.4 A.
Similarly, the ADTC can be applied in the negative direction.
OUTA, OUTD
OUTB, OUTC
SR1, I_SR1
LIGHT LOAD MODE AND DEEP LIGHT LOAD MODE
To facilitate efficiency over the load range, the following three
operation modes can be configured in the ADP1051, according to
the programmed CS2 current thresholds:
Normal mode. In normal mode, the SR PWM outputs are in
complement with the primary PWM outputs.
Light load mode. The SR PWM outputs still work, but they are in
phase with the primary PWMs.
Deep light load mode. All PWM outputs can be disabled.
Figure 16 shows the operation timing of a hard-switched full bridge
converter. When the CS2 current (output current) drops across the
light load mode threshold programmed by Register 0xFE19[3:0],
the SR1 and SR2 PWM signals switch from complementary mode
(normal mode) to in-phase mode (light load mode), as shown in
Figure 16.
SR2, I_SR2
Vp_T, Ip_T
LIGHT LOAD MODE
OUTA, OUTD
OUTB, OUTC
SR1, I_SR1
SR2, I_SR1
Vp_T, Ip_T
DEEP LIGHT LOAD
MODE
OUTA, OUTD
To achieve normal operation of light load mode, keep in mind the
following:
In a hard-switched full bridge topology having the same power stage
shown in Figure 12, if QA to QD are driven by OUTA to OUTD
separately, program the SR1 output in complement with OUTB and
OUTC in normal mode, and program the SR2 output in
complement with OUTA and OUTD, as shown in Figure 16. In
this case, the OUTA to OUTD outputs are all modulated.
In a zero-voltage-switched full bridge topology having the same
power stage shown in Figure 12 and the PWM settings shown in
Figure 13, SR1 is in complement with OUTC and SR2 is in
complement with OUTA in normal mode. In light load mode, SR1
is in phase with OUTA, and SR2 is in phase with OUTC.
If the hard-switched full bridge, half bridge, and push pull
topologies are used and the primary switches are controlled by
OUTA and OUTB only, SR1 is in complement with OUTB, and SR2
is in complement with OUTA in normal mode. Then, in the light
load mode, SR1 is in phase with OUTA, and SR2 is in phase with
OUTB.
When the CS2 current drops across the deep light load mode
threshold programmed by Register 0xFE1B[3:0], all PWM channels
can be disabled by Register 0xFE1C[5:0]. This allows the ADP1051
to be used in interleaved topologies, incorporating the automatic
phase shedding function in light load mode.
In both light load mode and deep light load mode, the CS2
averaging speed for the threshold can be set from 41 μs to 328 μs
in four discrete steps, using Register 0xFE1E[5:4]. The hysteresis
can be set by Register 0xFE1E[3:2].
OUTB, OUTC
SR1, I_SR1
SR2, I_SR2
Vp_T, Ip_T
Figure 16. Light Load Mode and Deep Light Load Mode
FREQUENCY SYNCHRONIZATION
The frequency synchronizing function of the ADP1051 includes
the synchronization input (SYNI) as a slave device and the
synchronization output (SYNO, using the OUTC or OUTD pin)
as a master device.
Synchronization as a Slave Device
The ADP1051 can be programmed to take the SYNI/FLGI pin signal
as the reference to synchronize the internal programmed PWM
clock with an external clock.
The frequency capture range requirement is for the period of the
external clock that is applied at the SYNI pin to be 90% to 110% of
the period of the internal programmed PWM clock. The minimum
pulse width of the SYNI signal is 360 ns. From the rising edge of the
SYNI signal to the start of the internal clock cycle, there is a 760 ns
propagation delay. Additional delay time is programmed, using
Register 0xFE11, to realize interleaving control with different
controllers.
To achieve a smooth synchronization transition between asynchro-
nous operation and synchronous operation, there is a phase capture
range bit for synchronization in Register 0xFE12[6] for capturing
Rev. B | Page 17 of 108
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