ADP3166JRU-REEL 데이터 시트보기 (PDF) - Analog Devices
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ADP3166JRU-REEL Datasheet PDF : 20 Pages
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5-Bit Programmable 2-, 3-, 4-Phase
Synchronous Buck Controller
ADP3166*
FEATURES
Selectable 2-, 3- or 4-Phase Operation at up to
1 MHz per Phase
Differential Sensing Error ±1% over Temperature
Logic-Level PWM Outputs for Interface to
External High Power Drivers
Active Current Balancing between All Output Phases
Built-in Power Good Blanking Supports On-the-Fly
VID Code Changes
5-Bit Digitally Programmable 0.8 V to 1.55 V Output
Short-Circuit Protection with Programmable
Latch-Off Delay
Overvoltage Protection Crowbar Logic Output
APPLICATIONS
Desktop PC Power Supplies
Next-Generation AMD Processors
VRM Modules
GENERAL DESCRIPTION
The ADP3166 is a highly efficient, multiphase, synchronous
buck switching regulator controller optimized for converting a
12 V main supply into the core supply voltage required by high
performance AMD processors. It uses an internal 5-bit DAC to
read a voltage identification (VID) code directly from the pro-
cessor, which is used to set the output voltage between 0.8 V
and 1.55 V. The ADP3166 also uses a multimode PWM
architecture to drive the logic-level outputs at a programmable
switching frequency that can be optimized for VRM size and
efficiency. The phase relationship of the output signals can be
programmed to provide 2-, 3-, or 4-phase operation, allowing
for the construction of up to four complementary buck switch-
ing stages.
The ADP3166 includes programmable no-load offset and slope
functions to adjust the output voltage as a function of the load
current so that it is always optimally positioned for a system
transient. The ADP3166 also provides accurate and reliable
short-circuit protection, adjustable current limiting, and a delayed
power good output that accommodates on-the-fly output volt-
age changes requested by the CPU.
ADP3166 is specified over the commercial temperature range of
0°C to 85°C and is available in a 28-lead TSSOP package.
FUNCTIONAL BLOCK DIAGRAM
VCC
28
ADP3166
EN 11
UVLO
SHUTDOWN
AND BIAS
GND 19
CROWBAR 6
CSREF +
2.1V –
DAC + 300mV +
CSREF
–
+
–
DAC – 300mV
PWRGD 10
DELAY
ILIMIT 15
EN
RAMPADJ RT
14
13
OSCILLATOR
CURRENT
BALANCING
CIRCUIT
+
–CMP
SET EN
RESET
27 PWM1
+
CMP
–
+
–CMP
RESET
2-, 3- , 4-PHASE
DRIVER LOGIC
RESET
26 PWM2
25 PWM3
+
–CMP
RESET
24 PWM4
CROWBAR
CURRENT
LIMIT
CURRENT
LIMIT
CIRCUIT
23 SW1
22 SW2
21 SW3
20 SW4
17 CSSUM
16 CSREF
DELAY 12
COMP 9
SOFT
START
18 CSCOMP
8 FB
+
–
PRECISION
REFERENCE
VID
DAC
7
FBRTN
1
2
3
4
5
VID4 VID3 VID2 VID1 VID0
*Patent pending
REV. 0
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