ADP3422JRU 데이터 시트보기 (PDF) - Analog Devices
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ADP3422JRU Datasheet PDF : 16 Pages
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ADP3422
Application Schematic
Figure 3 shows the simplified application schematic of the
ADP3422 control IC. The ADP3422, together with its com-
panion dual MOSFET driver IC, the ADP3415, controls a
hysteretic converter that generates the core voltage for the CPU.
Design Procedure—Power Stage Components
The first step of the converter design is to select the MOSFETs
to be used based on acceptable dc and switching losses. For this
selection, the designer is referred to the MOSFET manufac-
turers who may provide not only a recommendation for the
MOSFETs to be used for the specific application, but also
data and/or guidelines for determining an acceptable maxi-
mum operating frequency.
With this information, the next step is to choose an inductance
value—usually the smallest available value, that will yield an
acceptable ripple current. A ripple current 30%~60% of the
maximum core current is recommended. Inductance, frequency,
and ripple current are related by formula (6), derived from (5):
L=
1
(VIM – VVID )VVID
fMAX I RPP
VIM
(6)
where:
L = inductance value
fMAX = maximum acceptable switching frequency
IRPP = selected peak-to-peak ripple current
VIM = maximum input voltage
VVID = nominal programmed VID voltage
Assuming fMAX = 250 kHz, IRPP = 8 A, VIM = 20 V, and
VVID = 1.25 V, the required inductance value is L = 729 nH.
A standard value of 660 nH is available.
The next step is to select the current sensing resistor, RCS. The
restrictions are that (1) the resistance should not be higher than
the core converter output impedance defined by Intel’s IMVP-2
specification, and (2) the resistance should not be so low that
the errors in reading the current sense signal become a problem.
The IMVP-2 specification requires that the converter output
impedance, ROUT, be 4 mΩ. An RCS value of above one-quarter
of the nominal output impedance provides sufficient protection
against errors in the current sense signal. The chosen value is
RCS = 1.5 mΩ.
Also, the power dissipation, PCS, should be calculated to ensure
that a properly sized resistor is selected:
PCS = RCS IO2 ( MAX )
(7)
where IO(MAX) is the maximum output current. In this design
example IO(MAX) = 19 A. The resulting dissipation of the current
sense resistor is 542 mW.
The final step in finishing the design of the power stage is select-
ing the output capacitors. There are two primary considerations
in choosing those capacitors. The total ESR may not exceed the
output resistance required by Intel’s IMVP-2 specification. Also
the total capacitance must be checked to make sure that it is
sufficient to prevent overshoot beyond the voltage step caused
by the ESR during a full load transient, according to the formula:
CO( MIN )
=
L
× (IO( MAX ) – IO( MIN ))
ROUT × VL
(8)
where IO(MIN) is the minimum rated current for the normal
operation region of the CPU where IO(MAX) can occur, and VL is
the voltage applied across the inductor in order to ramp the
current in the direction of the load step. The minimum CPU
voltage represents a critical performance limit that must not be
violated during a load step increase. Therefore, the minimum
capacitance must never be less than the calculated value when
using VL = VI(MIN) – VVID in (8) the voltage applied across the
inductor to ramp up the current. However, overshoot would still
occur unless the capacitance is greater than the calculated value
when using VL = VVID in (8). The magnitude of the overshoot is
given by:
VOS =
[ ] L
CO
IO( MAX ) +
IRPP 2
2
–
IO2
(
MIN
)
+
VVID
–
ROUT IO( MAX ) 2
– VVID
(9)
For this design example, output capacitors with a capacitance
of 150 µF and a maximum ESR of 20 mΩ are chosen. Given
the target of ROUT = 4 mΩ, five capacitors would be needed to
achieve a total ESR of not more than 4 mΩ. The total capaci-
tance of five of these capacitors is 750 µF. This capacitance is
greater than the value required for a load step increase, even
for an input voltage as low as 6 V; but it is less than what is
needed to prevent an overshoot for a load step decrease, where
only the output voltage is applied across the inductor to ramp
down the current to the minimum value. Assuming that the
minimum current is zero, the overshoot above VVID is 89 mV.
Design Procedure—Control Circuit Components
The output resistance is implemented by using the proper ratio
of two resistors, which connect to the REG pin. One resistor,
RD, connects to the DAC reference and the other, RC, connects
to the core voltage. From (2):
RD = RE – RT – RCS
RC
RCS
(10)
where RT is the PCB trace resistance between the current sense
resistor and the CPU measurement point.
There is no inherent restriction on the absolute value of either
RD or RC, but values in the single kΩ range are recommended.
These resistors can now be selected.
–12–
REV. 0
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