ADS-939MM 데이터 시트보기 (PDF) - Murata Power Solutions
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ADS-939MM Datasheet PDF : 7 Pages
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ADS-939
16-Bit, 10MHz Sampling A/D Converters
DYNAMIC PERFORMANCE (Cont.)
ANALOG OUTPUT
Internal Reference
Voltage
Drift
External Current
DIGITAL OUTPUTS
Logic Levels
Logic "1"
Logic "0"
Logic Loading "1"
Logic Loading "0"
Output Coding
POWER REQUIREMENTS
Power Supply Ranges
+5V Supply
–5V Supply
+12V Supply
–12V Supply
+15V Supply
–15V Supply
MIN.
+25°C
TYP.
MAX.
0 TO +70°C
MIN.
TYP. MAX.
–55 TO +125°C
MIN. TYP.
MAX.
UNITS
—
+3.2
—
—
±30
—
—
5
—
—
+3.2
—
—
±30
—
—
5
—
—
+3.2
—
Volts
—
±30
—
ppm/°C
—
5
—
mA
+2.4
—
—
+2.4
—
—
+2.4
—
—
Volts
—
—
+0.4
—
—
+0.4
—
—
+0.4
Volts
—
—
–4
—
—
–4
—
—
–4
mA
—
—
+4
—
—
+4
—
—
+4
mA
(Offset) Binary / Complementary (Offset) Binary / Two's Complement / Complementary Two's Complement
+4.75
+5.0
+5.25
+4.75
+5.0
+5.25
+4.9
+5.0
+5.25
Volts
–4.75
–5.0
–5.25
–4.75
–5.0
–5.25
–4.9
–5.0
–5.25
Volts
+11.5
+12.0
+12.5
+11.5
+12.0
+12.5
+11.5
+12.0
+12.5
Volts
–11.5
–12.0
–12.5
–11.5
–12.0
–12.5
–11.5
–12.0
–12.5
Volts
+14.5
+15.0
+15.5
+14.5
+15.0
+15.5
+14.5
+15.0
+15.5
Volts
–14.5
–15.0
–15.5
–14.5
–15.0
–15.5
–14.5
–15.0
–15.5
Volts
Power Supply Currents
+5V Supply
–5V Supply
–12/15V Supply
+12/15V Supply
Power Dissipation
Power Supply Rejection
—
+50
—
—
TBD
—
—
TBD
—
mA
—
–36
—
—
TBD
—
—
TBD
—
mA
—
–25
—
—
TBD
—
—
TBD
—
mA
—
+70
—
—
TBD
—
—
TBD
—
mA
—
1.5
TBD
—
TBD
TBD
—
TBD
TBD
Watts
—
—
±0.07
—
—
±0.07
—
—
±0.07 %FSR/%V
Footnotes:
~ All power supplies must be on before applying a start convert pulse. All
supplies and the clock (START CONVERT) must be present during warm-up
periods. The device must be continuously converting during this time.
When COMP. BITS (pin 35) is low, logic loading "0" will be –350μA.
A 10MHz clock with a 50nsec positive pulse width is used for all production
testing. See Timing Diagram for more details.
This is the time required before the A/D output data is valid once the analog
input is back within the specified range.
See table 2a, Setting Output Coding Selection.
The minimum supply voltages of +4.9V and –4.9V for ±VDD are required for
–55°C operation only. The minimum limits are +4.75V and –4.75V when
operating at +125°C.
Effective bits is equal to:
Full Scale Amplitude
(SNR + Distortion) – 1.76 + 20 log
Actual Input Amplitude
±12V only or ±15V only required.
6.02
TECHNICAL NOTES
1. Obtaining fully specified performance from the ADS-939A requires
careful attention to pc-card layout and power supply decoupling. The
device's analog and digital ground systems are connected to each
other internally. For optimal performance, tie all ground pins (4, 7, 30
and 36) directly to a large analog ground plane beneath the package.
For the best performance it is recommended to use a single power
source for both the +5V analog and +5V digital supplies. Bypass all
power supplies and the +3.2V reference output to ground with 4.7μF
tantalum capacitors in parallel with 0.1μF ceramic capacitors. Locate
the bypass capacitors as close to the unit as possible.
2. The ADS-939A achieves its specified accuracies without the need
for external calibration. If required, the device's small initial offset
and gain errors can be reduced to zero using the adjustment circuitry
shown in Figure 2. When using this circuitry, or any similar offset and
gain calibration hardware, make adjustments following warm-up. To
avoid interaction, always adjust offset before gain. Tie pins 5 and 6 to
ANALOG GROUND (pin 4) if not using offset and gain adjust circuits.
3. Pin 35 (COMP. BITS) is used to select the digital output coding format
of the ADS-939A. See Tables 2a and 2b. When this pin has a TTL
logic "0" applied, it complements all of the ADS-939A’s digital outputs.
When pin 35 has a logic "1" applied, the output coding is comple-
mentary (offset) binary. Applying a logic "0" to pin 35 changes the
coding to (offset) binary. Using the MSB output (pin 29) instead of
the MSB output (pin 28) changes the respective output codings to
complementary two's
complement and two's complement.
Pin 35 is TTL compatible and can be directly driven with digital logic
in applications requiring dynamic control over its function. There
is an internal pull-up resistor on pin 35 allowing it to be either con-
nected to +5V or left open when a logic "1" is required.
4. To enable the three-state outputs, connect OUTPUT
ENABLE (pin 34) to a logic "0" (low). To disable, connect pin 34 to a
logic "1" (high).
5. Applying a start convert pulse while a conversion is in progress
(EOC = logic "1") will initiate a new and probably inaccurate conver-
sion cycle. Data from both the interrupted and subsequent conver-
sions will be invalid.
6. Do not enable/disable or complement the output bits or read from
the FIFO during the conversion process (from the rising edge of
EOC to the falling edge of EOC).
7. The OVERFLOW bit (pin 33) switches from 0 to 1 when the input
voltage exceeds that which produces an output of all 1’s or when
the input equals or exceeds the voltage that produces all 0’s. When
COMP BITS is activated, the above conditions are reversed.
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MDA_ADS-939.A01 Page 3 of 7
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