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ADXL210E

Low-Cost ±10 g Dual-Axis Accelerometer with Duty Cycle

Analog Devices 

ADXL210E

DESIGN PROCEDURE FOR THE ADXL210E

The design procedure for using the ADXL210E with a duty cycle

output involves selecting a duty cycle period and a filter capacitor.

A proper design will take into account the application requirements

for bandwidth, signal resolution and acquisition time, as discussed

in the following sections.

Decoupling Capacitor CDC

A 0.1 µF capacitor is recommended from VDD to COM for power

supply decoupling.

ST

The ST pin controls the self-test feature. When this pin is set to VDD,

an electrostatic force is exerted on the beam of the accelerometer.

The resulting movement of the beam allows the user to test if the

accelerometer is functional. The typical change in output will be 3%

at the duty cycle outputs (corresponding to 800 mg). This pin

may be left open circuit or connected to common in normal use.

Duty Cycle Decoding

The ADXL210E’s digital output is a duty cycle modulator.

Acceleration is proportional to the ratio T1/T2. The nominal

output of the ADXL210E is:

0 g = 50% Duty Cycle

Scale factor is 4% Duty Cycle Change per g

These nominal values are affected by the initial tolerance of the

device including zero g offset error and sensitivity error.

T2 does not have to be measured for every measurement cycle.

It need only be updated to account for changes due to tempera-

ture (a relatively slow process). Since the T2 time period is shared

by both X and Y channels, it is necessary only to measure it on

one channel of the ADXL210E. Decoding algorithms for various

microcontrollers have been developed. Consult the appropriate

Application Note.

3V TO 5.25V

VDD

CX

XFILT

SELF-TEST

X SENSOR

DEMOD

RFILT

32k⍀

ANALOG

XOUT

C

O

CDC

OSCILLATOR

ADXL210E

TO

DUTY

U

N ␮P

CYCLE

T

DEMOD

Y SENSOR

RFILT

32k⍀

(ADC)

E

YOUT

R

COM

YFILT

T2

CY

RSET

T2

T1

A(g) = (T1/T2 – 0.5)/4%

0g = 50% DUTY CYCLE

T2 = RSET/125M⍀

Figure 3. Block Diagram

Setting the Bandwidth Using CX and CY

The ADXL210E has provisions for bandlimiting the XFILT and

YFILT pins. Capacitors must be added at these pins to implement

low-pass filtering for antialiasing and noise reduction. The equa-

tion for the 3 dB bandwidth is:

( ) F–3 dB =

1

2 π (32 kΩ) × C(x, y)

or, more simply,

F–3 dB

= 5 µF

C(X ,Y )

The tolerance of the internal resistor (RFILT), can vary typically as

much as ± 15% of its nominal value of 32 kΩ; so the bandwidth

will vary accordingly. A minimum capacitance of 1000 pF for

C(X, Y) is required in all cases.

Table I. Filter Capacitor Selection, CX and CY

Bandwidth

Capacitor

Value

10 Hz

50 Hz

100 Hz

200 Hz

500 Hz

5 kHz

0.47 µF

0.10 µF

0.05 µF

0.027 µF

0.01 µF

0.001 µF

Setting the DCM Period with RSET

The period of the DCM output is set for both channels by a single

resistor from RSET to ground. The equation for the period is:

T 2 = RSET (Ω)

125 MΩ

A 125 kΩ resistor will set the duty cycle repetition rate to approxi-

mately 1 kHz, or 1 ms. The device is designed to operate at duty

cycle periods between 0.5 ms and 10 ms.

Table II. Resistor Values to Set T2

T2

1 ms

2 ms

5 ms

10 ms

RSET

125 kΩ

250 kΩ

625 kΩ

1.25 MΩ

Note that the RSET should always be included, even if only an

analog output is desired. Use an RSET value between 500 kΩ

and 2 MΩ when taking the output from XFILT or YFILT. The RSET

resistor should be placed close to the T2 Pin to minimize parasitic

capacitance at this node.

Selecting the Right Accelerometer

For most tilt sensing applications the ADXL202E is the most

appropriate accelerometer. Its higher sensitivity (12.5%/g) allows

the user to use a lower speed counter for PWM decoding while

maintaining high resolution. The ADXL210E should be used in

applications where accelerations of greater than ±2 g are expected.

REV. 0

–9–

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