AP2141FMG-7(2013) 데이터 시트보기 (PDF) - Diodes Incorporated.

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AP2141FMG-7
(Rev.:2013)

0.5A SINGLE CHANNEL CURRENT-LIMITED POWER SWITCH

Diodes Incorporated. 

AP2141/ AP2151

Electrical Characteristics (@TA = +25°C, VIN = +5.0V, unless otherwise specified.)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VUVLO Input UVLO

RLOAD = 1kΩ

1.6

1.9

2.5

V

ISHDN Input Shutdown Current

Disabled, IOUT = 0

0.5

1

µA

IQ Input Quiescent Current

Enabled, IOUT = 0

45

70

µA

ILEAK Input Leakage Current

Disabled, OUT grounded

1

µA

IREV Reverse Leakage Current

Disabled, VIN = 0V, VOUT = 5V, IREV at VIN

1

µA

RDS(ON) Switch On-Resistance

VIN = 5V,

IOUT = 0.5A

SOT25, SO-8, MSOP-8EP

TA = +25°C U-DFN2018-6

-40°C ≤ TA ≤ +85°C

95

115

90

110

140

mΩ

VIN = 3.3V, TA = +25°C

IOUT = 0.5A -40°C ≤ TA ≤ +85°C

120

140

170

ISHORT Short-Circuit Current Limit

Enabled into short circuit, CL = 22µF

0.6

A

ILIMIT Over-Load Current Limit

VIN = 5V, VOUT = 4.8V, CL = 22µF, -40C ≤ TA ≤ +85°C

0.6

0.8

1.0

A

ITRIG Current Limiting Trigger Threshold Output Current Slew rate (<100A/s) , CL = 22µF

1.0

A

ISINK EN Input Leakage

VEN = 5V

1

µA

tD(ON) Output Turn-On Delay Time

CL = 1µF, RLOAD = 10Ω

0.05

ms

tR Output Turn-On Rise Time

CL = 1µF, RLOAD = 10Ω

0.6

1.5

ms

tD(OFF) Output Turn-Off delay Time

CL = 1µF, RLOAD = 10Ω

0.01

ms

tF Output Turn-Off Fall Time

RFLG FLG Output FET On-Resistance

CL = 1µF, RLOAD = 10Ω

IFLG =10mA

0.05

0.1

ms

20

40

Ω

tBLANK FLG Blanking Time

CIN = 10µF, CL = 22µF

4

7

15

ms

TSHDN Thermal Shutdown Threshold

Enabled, RLOAD = 1kΩ

140

C

THYS Thermal Shutdown Hysteresis

SO-8 (Note 5)

25

C

110

oC/W

θJA

Thermal Resistance Junction-to-

Ambient

MSOP-8EP (Note 6)

SOT25 (Note 7)

60

oC/W

157

oC/W

U-DFN2018-6 (Note 8)

70

oC/W

Notes:

5. Test condition for SO-8: Device mounted on FR-4, 2oz copper, with minimum recommended pad layout.

6. Test condition for SO-8, MSOP-8EP: Device mounted on 2” x 2” FR-4 substrate PC board, 2oz copper, with minimum recommended pad on top layer

and thermal vias to bottom layer ground plane.

7. Test condition for SOT25: Device mounted on FR-4, 2oz copper, with minimum recommended pad layout.

8. Test condition for U-DFN2018-6: Device mounted on FR-4 2-layer board, 2oz copper, with minimum recommended pad on top layer and 3 vias to bottom

layer 1.0”x1.4” ground plane.

AP2141/ AP2151

Document number: DS31562 Rev. 7 - 2

4 of 17

www.diodes.com

March 2013

© Diodes Incorporated

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