APW7085K 데이터 시트보기 (PDF) - Anpec Electronics
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APW7085K Datasheet PDF : 24 Pages
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APW7085
Layout Consideration
In high power switching regulator, a correct layout is
important to ensure proper operation of the regulator. In
general, interconnecting impedance should be minimized
by using short and wide printed circuit traces. Signal and
power grounds are to be kept separating and fi-
nally combined using ground plane construction or
single point grounding. Figure 2 illustrates the layout,
with bold lines indicating high current paths. Components
along the bold lines should be placed close together.
Below is a checklist for your layout:
1. Begin the layout by placing the power components first.
Orient the power circuitry to achieve a clean power flow
path. If possible, make all the connections on one side
of the PCB with wide and copper filled areas.
2. In Figure 2, the loops with same color bold lines con-
duct high slew rate current. These interconnecting im-
pedances should be minimized by using wide and short
printed circuit traces.
3. Keep the sensitive small signal nodes (FB, COMP)
away from switching nodes (LX or others) on the PCB.
Therefore, place the feedback divider and the feedback
compensation network close to the IC to avoid switch-
ing noise. Connect the ground of feedback divider
directly to the GND pin of the IC using a dedicated
ground trace.
4. The VCC decoupling capacitor should be right next
to the VCC and GND pins. Capacitor C2 should be
connected as close to the VIN and UGND pins as
possible.
5. Place the decoupling ceramic capacitor C1 near the
VIN as close as possible. The bulk capacitors C8 are
also placed near VIN. Use a wide power ground plane
to connect the C1, C8, C4, and Schottky diode to pro-
vide a low impedance path between the components
for large and high slew rate current.
SOP-8
VLX
VIN
L1
VOUT
Load
GND
GND
Figure 3. Recommended Layout Diagram
+
VIN
-
C2
C3
C6 R4
C5
Compensation
Network
1
VIN
3 UGND LX 5
4 VCC
U1
2
APW7085
EN
6 COMP
FB 7
GND
8
C1 C8 L1
D1
R1
R2 C7
(Optional)
Feedback
Divider
+
C4 Load VOUT
-
Figure 2. Current Path Diagram
Copyright © ANPEC Electronics Corp.
19
Rev. A.7 - Sep., 2010
www.anpec.com.tw
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