AS7C256A-20JI 데이터 시트보기 (PDF) - Alliance Semiconductor

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AS7C256A-20JI

5V 32K X 8 CMOS SRAM (Common I/O)

Alliance Semiconductor 

AS7C256A

®

Read cycle (over the operating range)2,8

-10

Parameter

Symbol Min Max

Read cycle time

Address access time

tRC

10 –

tAA

– 10

Chip enable (CE) access time

tACE

– 10

Output enable (OE) access time tOE

–

5

Output hold from address change tOH

3

–

CE LOW to output in low Z

tCLZ

3

–

CE HIGH to output in high Z

tCHZ

–

3

OE LOW to output in low Z

tOLZ

0

–

OE HIGH to output in high Z

Power up time

Power down time

tOHZ

tPU

tPD

–

3

0

–

– 10

-12

Min Max

12 –

– 12

– 12

–

6

3

–

3

–

–

3

0

–

–

3

0

–

– 12

-15

Min Max

15 –

– 15

– 15

–

7

3

–

3

–

–

4

0

–

–

4

0

–

– 15

-20

Min Max

20 –

– 20

– 20

–

8

3

–

3

–

–

5

0

–

–

5

0

–

– 20

Unit Notes

ns

ns 2

ns 2

ns

ns 4

ns 3,4

ns 3,4

ns 3,4

ns 3,4

ns 3,4

ns 3,4

Key to switching waveforms

Rising input

Falling input

Undefined output/don’t care

Read waveform 1 (address controlled)2,5,6,8

tRC

Address

tAA

tOH

Dout

Data valid

Read waveform 2 (CE controlled)2,5,7,8

tRC1

CE

tOE

OE

tOLZ

tOHZ

tACE

tCHZ

Dout

Data valid

Supply

current

tCLZ

tPU

50%

tPD

ICC

50%

ISB

9/24/04; v.1.2

Alliance Semiconductor

P. 4 of 9

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