Figure 1-1. Block Diagram
2. Pin Configurations
Table 2-1.
Pin Name
CLK
IN
I/O
VCC
Pin Configurations (All Pinouts Top View)
Function
Clock
Logic Inputs
Bi-directional Buffers
+5V Supply
Figure 2-1. TSSOP
CLK/IN 1
IN 2
IN 3
IN 4
IN 5
IN 6
IN 7
IN 8
IN 9
IN 10
IN 11
GND 12
Figure 2-3. PLCC
24 VCC
23 I/O
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 IN
Figure 2-2. DIP/SOIC
CLK/IN 1
IN 2
IN 3
IN 4
IN 5
IN 6
IN 7
IN 8
IN 9
IN 10
IN 11
GND 12
24 VCC
23 I/O
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 IN
IN 5
IN 6
IN 7
GND* 8
IN 9
IN 10
IN 11
25 I/O
24 I/O
23 I/O
22 GND*
21 I/O
20 I/O
19 I/O
Note:
For PLCC, P1, P8, P15 and P22 can be
left unconnected. For superior perfor-
mance, connect VCC to pin 1 and GND
to 8, 15, and 22.
2 ATF22V10C(Q)Z
0778J–PLD–11/07