ATF22V10CZ-15SC 데이터 시트보기 (PDF) - Atmel Corporation

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ATF22V10CZ-15SC

High performance EE PLD

Atmel Corporation 

ATF22V10C(Q)Z

10. Functional Logic Diagram Description

The Functional Logic Diagram describes the ATF22V10CZ/CQZ architecture.

The ATF22V10CZ/CQZ has 12 inputs and 10 I/O macrocells. Each macrocell can be configured

into one of four output configurations: active high/low, registered/combinatorial output.The uni-

versal architecture of the ATF22V10CZ/CQZ can be programmed to emulate most 24-pin PAL

devices.

Unused product terms are automatically disabled by the compiler to decrease power consump-

tion. A security fuse, when programmed, protects the contents of the ATF22V10CZ/CQZ. Eight

bytes (64 fuses) of User Signature are accessible to the user for purposes such as storing

project name, part number, revision or date. The User Signature is accessible regardless of the

state of the security fuse.

9

0778J–PLD–11/07

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