MUAA2K80-20QGC 데이터 시트보기 (PDF) - Music Semiconductors
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MUAA2K80-20QGC Datasheet PDF : 18 Pages
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MUAA Routing Co-Processor (RCP) Family
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• High-performance MAC Address processor for
multiport switches and routers (up to 48 10/100Mb or
4 Gigabit Ethernet at wire speed)
• Layer 4 flow recognition for Quality of Service up to
16.7 million packets per second
• ARP cache manager/IP address caching at 12.5
million packets per second
• Synchronous interfaces and programmable priority
between ports for simplicity of design
• Learn, age, and auto-age functions with “virtual
queues” keeping track of aged and learned entries
• Transparent cascade of up to four devices without
external logic, software setup, or performance hit
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• 2K and 8K x 80-bit partitionable CAM/RAM data
field in address database
• 32-bit synchronous port with separate inputs and
outputs; optional 16-bit configuration
• 32-bit bi-directional processor port; optional 16-bit
configuration
• Pipelined operation
• Operations performed from the synchronous port or
processor port; all flags independently available to
both ports
• 9-bit internal time stamp
• 50 MHz clock
• 160-pin PQFP package
• 3.3 Volt core with 3.3 Volt/5 Volt tolerant IO buffers
• IEEE 1149.1 (JTAG) compliant
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