C8051F043 데이터 시트보기 (PDF) - Silicon Laboratories

부품명

상세내역

제조사

C8051F043

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

Table 25.1. Boundary Data Register Bit Definitions (Continued)

EXTEST provides access to both capture and update actions, while Sample only performs a capture.

Bit

Action Target

75, 77, 79, 81, 83, Capture P4.n input from pin

85, 87, 89

Update P4.n output to pin

90, 92, 94, 96, 98, Capture P5.n output enable from MCU

100, 102, 104

Update P5.n output enable to pin

91, 93, 95, 97, 99, Capture P5.n input from pin

101, 103, 105

Update P5.n output to pin

106, 108, 110, 112, Capture P6.n output enable from MCU

114, 116, 118, 120 Update P6.n output enable to pin

107, 109, 111, 113, Capture P6.n input from pin

115, 117, 119, 121 Update P6.n output to pin

122, 124, 126, 128, Capture P7.n output enable from MCU

130, 132, 134, 136 Update P7.n output enable to pin

123, 125, 127, 129, Capture P7.n input from pin

131, 133, 135, 137 Update P7.n output to pin

25.1.1. EXTEST Instruction

The EXTEST instruction is accessed via the IR. The Boundary DR provides control and observability of all

the device pins as well as the Weak Pullup feature. All inputs to on-chip logic are set to logic 1.

25.1.2. SAMPLE Instruction

The SAMPLE instruction is accessed via the IR. The Boundary DR provides observability and presetting of

the scan-path latches.

25.1.3. BYPASS Instruction

The BYPASS instruction is accessed via the IR. It provides access to the standard JTAG Bypass data reg-

ister.

25.1.4. IDCODE Instruction

The IDCODE instruction is accessed via the IR. It provides access to the 32-bit Device ID register.

Rev. 1.5

319

Share Link: